Mercurial > repos > blastem
annotate m68k_to_x86.c @ 106:1eba2b9455f8
Implement ORI to CCR/SR
author | Mike Pavone <pavone@retrodev.com> |
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date | Fri, 28 Dec 2012 11:07:13 -0800 |
parents | 1a0fd122ca8f |
children | 9705075fcf36 |
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1 #include "gen_x86.h" |
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2 #include "m68k_to_x86.h" |
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3 #include "mem.h" |
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4 #include <stdio.h> |
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5 #include <stddef.h> |
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6 #include <stdlib.h> |
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7 #include <string.h> |
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8 |
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9 #define BUS 4 |
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10 #define PREDEC_PENALTY 2 |
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11 #define CYCLES RAX |
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12 #define LIMIT RBP |
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13 #define SCRATCH1 RCX |
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14 #define SCRATCH2 RDI |
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15 #define CONTEXT RSI |
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16 |
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17 #define FLAG_N RBX |
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18 #define FLAG_V BH |
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19 #define FLAG_Z RDX |
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20 #define FLAG_C DH |
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21 |
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22 typedef struct { |
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23 int32_t disp; |
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24 uint8_t mode; |
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25 uint8_t base; |
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26 uint8_t index; |
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27 uint8_t cycles; |
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28 } x86_ea; |
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29 |
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30 void handle_cycle_limit_int(); |
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31 void m68k_read_word_scratch1(); |
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32 void m68k_read_long_scratch1(); |
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33 void m68k_read_byte_scratch1(); |
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34 void m68k_write_word(); |
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35 void m68k_write_long_lowfirst(); |
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36 void m68k_write_long_highfirst(); |
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37 void m68k_write_byte(); |
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38 void m68k_save_context(); |
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39 void m68k_modified_ret_addr(); |
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40 void m68k_native_addr(); |
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41 void m68k_native_addr_and_sync(); |
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42 void set_sr(); |
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43 void set_ccr(); |
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44 void get_sr(); |
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45 void m68k_start_context(uint8_t * addr, m68k_context * context); |
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46 |
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47 uint8_t * cycles(uint8_t * dst, uint32_t num) |
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48 { |
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49 dst = add_ir(dst, num, CYCLES, SZ_D); |
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50 } |
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51 |
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52 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address) |
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53 { |
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54 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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55 uint8_t * jmp_off = dst+1; |
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56 dst = jcc(dst, CC_NC, dst + 7); |
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57 dst = mov_ir(dst, address, SCRATCH1, SZ_D); |
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58 dst = call(dst, (uint8_t *)handle_cycle_limit_int); |
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59 *jmp_off = dst - (jmp_off+1); |
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60 return dst; |
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61 } |
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62 |
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63 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) |
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64 { |
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65 if (op->addr_mode == MODE_REG) { |
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66 return opts->dregs[op->params.regs.pri]; |
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67 } |
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68 if (op->addr_mode == MODE_AREG) { |
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69 return opts->aregs[op->params.regs.pri]; |
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70 } |
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71 return -1; |
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72 } |
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73 |
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74 //must be called with an m68k_op_info that uses a register |
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75 size_t reg_offset(m68k_op_info *op) |
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76 { |
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77 if (op->addr_mode == MODE_REG) { |
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78 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri; |
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79 } |
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80 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri; |
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81 } |
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82 |
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83 void print_regs_exit(m68k_context * context) |
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84 { |
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85 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]); |
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86 for (int i = 0; i < 8; i++) { |
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87 printf("d%d: %X\n", i, context->dregs[i]); |
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88 } |
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89 for (int i = 0; i < 8; i++) { |
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90 printf("a%d: %X\n", i, context->aregs[i]); |
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91 } |
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92 exit(0); |
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93 } |
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94 |
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95 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts) |
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96 { |
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97 int8_t reg = native_reg(&(inst->src), opts); |
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98 uint8_t sec_reg; |
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99 int32_t dec_amount,inc_amount; |
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100 if (reg >= 0) { |
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101 ea->mode = MODE_REG_DIRECT; |
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102 ea->base = reg; |
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103 return out; |
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104 } |
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105 switch (inst->src.addr_mode) |
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106 { |
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107 case MODE_REG: |
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108 case MODE_AREG: |
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109 //We only get one memory parameter, so if the dst operand is a register in memory, |
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110 //we need to copy this to a temp register first |
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111 reg = native_reg(&(inst->dst), opts); |
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112 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode == MODE_AREG) |
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113 || inst->op == M68K_EXG) { |
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114 |
18
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115 ea->mode = MODE_REG_DISPLACE8; |
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116 ea->base = CONTEXT; |
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117 ea->disp = reg_offset(&(inst->src)); |
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118 } else { |
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119 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size); |
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120 ea->mode = MODE_REG_DIRECT; |
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121 ea->base = SCRATCH1; |
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122 } |
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123 break; |
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124 case MODE_AREG_PREDEC: |
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125 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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126 out = cycles(out, PREDEC_PENALTY); |
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127 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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128 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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129 } else { |
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130 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
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131 } |
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132 case MODE_AREG_INDIRECT: |
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133 case MODE_AREG_POSTINC: |
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134 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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135 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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136 } else { |
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137 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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138 } |
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139 switch (inst->extra.size) |
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140 { |
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141 case OPSIZE_BYTE: |
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142 out = call(out, (char *)m68k_read_byte_scratch1); |
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143 break; |
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144 case OPSIZE_WORD: |
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145 out = call(out, (char *)m68k_read_word_scratch1); |
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146 break; |
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147 case OPSIZE_LONG: |
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148 out = call(out, (char *)m68k_read_long_scratch1); |
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149 break; |
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150 } |
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151 |
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152 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
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153 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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154 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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155 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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156 } else { |
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157 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
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158 } |
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159 } |
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160 ea->mode = MODE_REG_DIRECT; |
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161 ea->base = SCRATCH1; |
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162 break; |
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163 case MODE_AREG_DISPLACE: |
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164 out = cycles(out, BUS); |
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165 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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166 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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167 } else { |
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168 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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169 } |
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170 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
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171 switch (inst->extra.size) |
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172 { |
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173 case OPSIZE_BYTE: |
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174 out = call(out, (char *)m68k_read_byte_scratch1); |
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175 break; |
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176 case OPSIZE_WORD: |
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177 out = call(out, (char *)m68k_read_word_scratch1); |
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178 break; |
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179 case OPSIZE_LONG: |
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180 out = call(out, (char *)m68k_read_long_scratch1); |
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181 break; |
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182 } |
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183 ea->mode = MODE_REG_DIRECT; |
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184 ea->base = SCRATCH1; |
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185 break; |
81
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186 case MODE_AREG_INDEX_DISP8: |
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187 out = cycles(out, 6); |
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188 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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189 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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190 } else { |
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191 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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192 } |
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193 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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194 if (inst->src.params.regs.sec & 1) { |
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195 if (inst->src.params.regs.sec & 0x10) { |
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196 if (opts->aregs[sec_reg] >= 0) { |
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197 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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198 } else { |
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199 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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200 } |
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201 } else { |
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202 if (opts->dregs[sec_reg] >= 0) { |
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203 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
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204 } else { |
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205 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
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206 } |
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207 } |
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208 } else { |
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209 if (inst->src.params.regs.sec & 0x10) { |
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210 if (opts->aregs[sec_reg] >= 0) { |
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211 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
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212 } else { |
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|
213 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
214 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
215 } else { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
216 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
217 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
218 } else { |
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
219 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
220 } |
6d231dbe75ab
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78
diff
changeset
|
221 } |
6d231dbe75ab
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diff
changeset
|
222 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
223 } |
6d231dbe75ab
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78
diff
changeset
|
224 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
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diff
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|
225 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
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|
226 } |
97
c7185fd840fc
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96
diff
changeset
|
227 switch (inst->extra.size) |
c7185fd840fc
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96
diff
changeset
|
228 { |
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96
diff
changeset
|
229 case OPSIZE_BYTE: |
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96
diff
changeset
|
230 out = call(out, (char *)m68k_read_byte_scratch1); |
c7185fd840fc
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96
diff
changeset
|
231 break; |
c7185fd840fc
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96
diff
changeset
|
232 case OPSIZE_WORD: |
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diff
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|
233 out = call(out, (char *)m68k_read_word_scratch1); |
c7185fd840fc
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diff
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|
234 break; |
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diff
changeset
|
235 case OPSIZE_LONG: |
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diff
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|
236 out = call(out, (char *)m68k_read_long_scratch1); |
c7185fd840fc
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diff
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|
237 break; |
c7185fd840fc
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diff
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|
238 } |
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|
239 ea->mode = MODE_REG_DIRECT; |
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96
diff
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|
240 ea->base = SCRATCH1; |
81
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diff
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|
241 break; |
71
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70
diff
changeset
|
242 case MODE_PC_DISPLACE: |
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diff
changeset
|
243 out = cycles(out, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
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73
diff
changeset
|
244 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
71
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70
diff
changeset
|
245 switch (inst->extra.size) |
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70
diff
changeset
|
246 { |
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70
diff
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|
247 case OPSIZE_BYTE: |
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diff
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|
248 out = call(out, (char *)m68k_read_byte_scratch1); |
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70
diff
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|
249 break; |
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70
diff
changeset
|
250 case OPSIZE_WORD: |
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70
diff
changeset
|
251 out = call(out, (char *)m68k_read_word_scratch1); |
f80fa1776507
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70
diff
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|
252 break; |
f80fa1776507
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70
diff
changeset
|
253 case OPSIZE_LONG: |
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diff
changeset
|
254 out = call(out, (char *)m68k_read_long_scratch1); |
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70
diff
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|
255 break; |
f80fa1776507
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70
diff
changeset
|
256 } |
f80fa1776507
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70
diff
changeset
|
257 ea->mode = MODE_REG_DIRECT; |
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diff
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|
258 ea->base = SCRATCH1; |
f80fa1776507
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diff
changeset
|
259 break; |
81
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diff
changeset
|
260 case MODE_PC_INDEX_DISP8: |
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78
diff
changeset
|
261 out = cycles(out, 6); |
96
f894f85cf39d
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95
diff
changeset
|
262 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
81
6d231dbe75ab
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78
diff
changeset
|
263 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
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78
diff
changeset
|
264 if (inst->src.params.regs.sec & 1) { |
6d231dbe75ab
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diff
changeset
|
265 if (inst->src.params.regs.sec & 0x10) { |
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diff
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|
266 if (opts->aregs[sec_reg] >= 0) { |
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changeset
|
267 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
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Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
268 } else { |
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Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
269 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
270 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
271 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
272 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
273 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
274 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
275 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
276 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
277 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
278 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
279 if (inst->src.params.regs.sec & 0x10) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
280 if (opts->aregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
281 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
282 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
283 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
284 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
285 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
286 if (opts->dregs[sec_reg] >= 0) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
287 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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parents:
78
diff
changeset
|
288 } else { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
289 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
290 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
291 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
292 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
293 } |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
294 if (inst->src.params.regs.displacement) { |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
295 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
296 } |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
297 switch (inst->extra.size) |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
298 { |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
299 case OPSIZE_BYTE: |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
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parents:
95
diff
changeset
|
300 out = call(out, (char *)m68k_read_byte_scratch1); |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
301 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
302 case OPSIZE_WORD: |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
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parents:
95
diff
changeset
|
303 out = call(out, (char *)m68k_read_word_scratch1); |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
304 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
305 case OPSIZE_LONG: |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
306 out = call(out, (char *)m68k_read_long_scratch1); |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
307 break; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
308 } |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
309 ea->mode = MODE_REG_DIRECT; |
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
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parents:
95
diff
changeset
|
310 ea->base = SCRATCH1; |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
311 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
312 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
313 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
314 if (inst->src.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
315 out = cycles(out, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
316 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
317 out = cycles(out, BUS); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
318 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
319 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
320 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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53
diff
changeset
|
321 { |
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diff
changeset
|
322 case OPSIZE_BYTE: |
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diff
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|
323 out = call(out, (char *)m68k_read_byte_scratch1); |
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53
diff
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|
324 break; |
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|
325 case OPSIZE_WORD: |
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|
326 out = call(out, (char *)m68k_read_word_scratch1); |
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diff
changeset
|
327 break; |
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changeset
|
328 case OPSIZE_LONG: |
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|
329 out = call(out, (char *)m68k_read_long_scratch1); |
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diff
changeset
|
330 break; |
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diff
changeset
|
331 } |
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changeset
|
332 ea->mode = MODE_REG_DIRECT; |
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diff
changeset
|
333 ea->base = SCRATCH1; |
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diff
changeset
|
334 break; |
18
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14
diff
changeset
|
335 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
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59
diff
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|
336 case MODE_IMMEDIATE_WORD: |
18
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|
337 if (inst->variant != VAR_QUICK) { |
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
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61
diff
changeset
|
338 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
18
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339 } |
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|
340 ea->mode = MODE_IMMED; |
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341 ea->disp = inst->src.params.immed; |
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342 break; |
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|
343 default: |
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344 printf("address mode %d not implemented (src)\n", inst->src.addr_mode); |
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345 exit(1); |
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346 } |
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347 return out; |
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348 } |
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|
349 |
92
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|
350 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read) |
18
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|
351 { |
98
104e257fb93c
Allow indexed modes to be used as a destination
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97
diff
changeset
|
352 int8_t reg = native_reg(&(inst->dst), opts), sec_reg; |
18
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|
353 int32_t dec_amount, inc_amount; |
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|
354 if (reg >= 0) { |
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|
355 ea->mode = MODE_REG_DIRECT; |
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|
356 ea->base = reg; |
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|
357 return out; |
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|
358 } |
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|
359 switch (inst->dst.addr_mode) |
14
2bdad0f52f42
x86 code gen, initial work on translator
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parents:
diff
changeset
|
360 { |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
361 case MODE_REG: |
2bdad0f52f42
x86 code gen, initial work on translator
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parents:
diff
changeset
|
362 case MODE_AREG: |
18
3e7bfde7606e
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|
363 ea->mode = MODE_REG_DISPLACE8; |
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|
364 ea->base = CONTEXT; |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
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51
diff
changeset
|
365 ea->disp = reg_offset(&(inst->dst)); |
18
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14
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|
366 break; |
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|
367 case MODE_AREG_PREDEC: |
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|
368 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
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|
369 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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|
370 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
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|
371 } else { |
52
f02ba3808757
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51
diff
changeset
|
372 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
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14
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|
373 } |
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14
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|
374 case MODE_AREG_INDIRECT: |
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|
375 case MODE_AREG_POSTINC: |
92
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87
diff
changeset
|
376 if (fake_read) { |
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87
diff
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|
377 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4); |
18
3e7bfde7606e
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14
diff
changeset
|
378 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
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87
diff
changeset
|
379 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
c3d034e076ee
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87
diff
changeset
|
380 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
c3d034e076ee
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87
diff
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|
381 } else { |
c3d034e076ee
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87
diff
changeset
|
382 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
383 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
384 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
385 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
386 case OPSIZE_BYTE: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
387 out = call(out, (char *)m68k_read_byte_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
388 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
389 case OPSIZE_WORD: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
390 out = call(out, (char *)m68k_read_word_scratch1); |
c3d034e076ee
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Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
391 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
392 case OPSIZE_LONG: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
393 out = call(out, (char *)m68k_read_long_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
394 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
395 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
396 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
397 //save reg value in SCRATCH2 so we can use it to save the result in memory later |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
398 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
399 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
400 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
401 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
402 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
403 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
404 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
405 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
406 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
407 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
408 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
409 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
410 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
411 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
412 ea->mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
413 ea->base = SCRATCH1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
414 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
415 case MODE_AREG_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
416 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
417 reg = fake_read ? SCRATCH2 : SCRATCH1; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
418 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
419 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
420 } else { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
421 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
422 } |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
423 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
424 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
425 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
426 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
427 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
428 case OPSIZE_BYTE: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
429 out = call(out, (char *)m68k_read_byte_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
430 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
431 case OPSIZE_WORD: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
432 out = call(out, (char *)m68k_read_word_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
433 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
434 case OPSIZE_LONG: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
435 out = call(out, (char *)m68k_read_long_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
436 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
437 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
438 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
439 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
440 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
441 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
442 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
443 case MODE_AREG_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
444 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
445 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
446 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
447 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
448 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
449 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
450 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
451 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
452 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
453 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
454 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
455 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
456 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
457 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
458 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
459 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
460 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
461 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
462 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
463 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
464 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
465 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
466 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
467 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
468 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
469 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
470 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
471 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
472 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
473 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
474 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
475 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
476 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
477 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
478 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
479 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
480 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
481 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
482 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
483 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
484 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
485 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
486 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
487 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
488 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
489 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
490 case OPSIZE_BYTE: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
491 out = call(out, (char *)m68k_read_byte_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
492 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
493 case OPSIZE_WORD: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
494 out = call(out, (char *)m68k_read_word_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
495 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
496 case OPSIZE_LONG: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
497 out = call(out, (char *)m68k_read_long_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
498 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
499 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
500 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
501 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
502 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
503 ea->base = SCRATCH1; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
504 case MODE_PC_DISPLACE: |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
505 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
506 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
507 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
508 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
509 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
510 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
511 case OPSIZE_BYTE: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
512 out = call(out, (char *)m68k_read_byte_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
513 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
514 case OPSIZE_WORD: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
515 out = call(out, (char *)m68k_read_word_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
516 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
517 case OPSIZE_LONG: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
518 out = call(out, (char *)m68k_read_long_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
519 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
520 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
521 out = pop_r(out, SCRATCH2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
522 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
523 ea->mode = MODE_REG_DIRECT; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
524 ea->base = SCRATCH1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
525 break; |
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
526 case MODE_PC_INDEX_DISP8: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
527 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
528 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
529 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
530 if (inst->dst.params.regs.sec & 1) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
531 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
532 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
533 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
534 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
535 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
536 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
537 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
538 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
539 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
540 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
541 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
542 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
543 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
544 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
545 if (inst->dst.params.regs.sec & 0x10) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
546 if (opts->aregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
547 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
548 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
549 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
550 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
551 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
552 if (opts->dregs[sec_reg] >= 0) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
553 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
554 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
555 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
556 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
557 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
558 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
559 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
560 if (inst->dst.params.regs.displacement) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
561 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
562 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
563 if (fake_read) { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
564 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
565 } else { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
566 out = push_r(out, SCRATCH1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
567 switch (inst->extra.size) |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
568 { |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
569 case OPSIZE_BYTE: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
570 out = call(out, (char *)m68k_read_byte_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
571 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
572 case OPSIZE_WORD: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
573 out = call(out, (char *)m68k_read_word_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
574 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
575 case OPSIZE_LONG: |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
576 out = call(out, (char *)m68k_read_long_scratch1); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
577 break; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
578 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
579 out = pop_r(out, SCRATCH2); |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
580 } |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
581 ea->mode = MODE_REG_DIRECT; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
582 ea->base = SCRATCH1; |
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
583 break; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
584 case MODE_ABSOLUTE: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
585 case MODE_ABSOLUTE_SHORT: |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
586 //Add cycles for reading address from instruction stream |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
587 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : 0)); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
588 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
589 if (!fake_read) { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
590 out = push_r(out, SCRATCH1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
591 switch (inst->extra.size) |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
592 { |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
593 case OPSIZE_BYTE: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
594 out = call(out, (char *)m68k_read_byte_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
595 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
596 case OPSIZE_WORD: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
597 out = call(out, (char *)m68k_read_word_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
598 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
599 case OPSIZE_LONG: |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
600 out = call(out, (char *)m68k_read_long_scratch1); |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
601 break; |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
602 } |
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
603 out = pop_r(out, SCRATCH2); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
604 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
605 ea->mode = MODE_REG_DIRECT; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
606 ea->base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
607 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
608 default: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
609 printf("address mode %d not implemented (dst)\n", inst->dst.addr_mode); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
610 exit(1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
611 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
612 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
613 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
614 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
615 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
616 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
617 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
618 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
619 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
620 case OPSIZE_BYTE: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
621 out = call(out, (char *)m68k_write_byte); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
622 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
623 case OPSIZE_WORD: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
624 out = call(out, (char *)m68k_write_word); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
625 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
626 case OPSIZE_LONG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
627 out = call(out, (char *)m68k_write_long_lowfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
628 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
629 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
630 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
631 return out; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
632 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
633 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
634 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
635 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
636 address &= 0xFFFFFF; |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
637 if (address > 0x400000) { |
86
3d3966c254b2
RTE doesn't crash the emulator anymore
Mike Pavone <pavone@retrodev.com>
parents:
82
diff
changeset
|
638 printf("get_native_address: %X\n", address); |
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
639 } |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
640 address /= 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
641 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
642 if (!native_code_map[chunk].base) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
643 return NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
644 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
645 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
646 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
647 return NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
648 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
649 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
650 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
651 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
652 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
653 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
654 deferred_addr * new_head = malloc(sizeof(deferred_addr)); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
655 new_head->next = old_head; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
656 new_head->address = address & 0xFFFFFF; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
657 new_head->dest = dest; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
658 return new_head; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
659 } |
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|
660 |
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14
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|
661 void process_deferred(x86_68k_options * opts) |
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14
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|
662 { |
3e7bfde7606e
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|
663 deferred_addr * cur = opts->deferred; |
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diff
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|
664 deferred_addr **last_next = &(opts->deferred); |
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14
diff
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|
665 while(cur) |
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diff
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|
666 { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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diff
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|
667 uint8_t * native = get_native_address(opts->native_code_map, cur->address); |
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|
668 if (native) { |
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14
diff
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|
669 int32_t disp = native - (cur->dest + 4); |
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14
diff
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|
670 uint8_t * out = cur->dest; |
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diff
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|
671 *(out++) = disp; |
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14
diff
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|
672 disp >>= 8; |
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14
diff
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|
673 *(out++) = disp; |
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diff
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|
674 disp >>= 8; |
3e7bfde7606e
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14
diff
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|
675 *(out++) = disp; |
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14
diff
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|
676 disp >>= 8; |
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14
diff
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|
677 *out = disp; |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
678 *last_next = cur->next; |
3e7bfde7606e
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14
diff
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|
679 free(cur); |
3e7bfde7606e
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14
diff
changeset
|
680 cur = *last_next; |
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parents:
14
diff
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|
681 } else { |
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14
diff
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|
682 last_next = &(cur->next); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
683 cur = cur->next; |
3e7bfde7606e
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14
diff
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|
684 } |
3e7bfde7606e
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14
diff
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|
685 } |
3e7bfde7606e
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14
diff
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|
686 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
687 |
3e7bfde7606e
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14
diff
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|
688 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr) |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
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|
689 { |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
690 address &= 0xFFFFFF; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
691 address/= 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
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|
692 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
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|
693 if (!native_code_map[chunk].base) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
694 native_code_map[chunk].base = native_addr; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
695 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
696 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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14
diff
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|
697 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
698 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
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|
699 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
700 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
701 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
702 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
703 { |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
704 int8_t reg, flags_reg, sec_reg; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
705 uint8_t dir = 0; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
706 int32_t offset; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
707 int32_t inc_amount, dec_amount; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
708 x86_ea src; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
709 dst = translate_m68k_src(inst, &src, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
710 reg = native_reg(&(inst->dst), opts); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
711 //update statically set flags |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
712 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
713 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
714 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
715 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
716 flags_reg = src.base; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
717 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
718 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
719 flags_reg = reg; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
720 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
721 dst = mov_ir(dst, src.disp, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
722 src.mode = MODE_REG_DIRECT; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
723 flags_reg = src.base = SCRATCH1; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
724 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
725 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
726 switch(inst->dst.addr_mode) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
727 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
728 case MODE_REG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
729 case MODE_AREG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
730 if (reg >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
731 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
732 dst = mov_rr(dst, src.base, reg, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
733 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
734 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
735 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
736 dst = mov_ir(dst, src.disp, reg, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
737 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
738 } else if(src.mode == MODE_REG_DIRECT) { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
739 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
740 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
741 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
742 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
743 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
744 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
745 dst = setcc_r(dst, CC_S, FLAG_N); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
747 case MODE_AREG_PREDEC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
748 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
749 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
750 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
751 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
752 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
753 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 case MODE_AREG_INDIRECT: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
755 case MODE_AREG_POSTINC: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
756 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
757 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
758 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
759 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
760 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
761 if (src.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
762 if (src.base != SCRATCH1) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
763 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
764 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
765 } else if (src.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
766 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
767 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
768 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
769 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
770 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
771 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
772 dst = setcc_r(dst, CC_S, FLAG_N); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
773 switch (inst->extra.size) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
774 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
775 case OPSIZE_BYTE: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
776 dst = call(dst, (char *)m68k_write_byte); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
777 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
778 case OPSIZE_WORD: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
779 dst = call(dst, (char *)m68k_write_word); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
780 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
781 case OPSIZE_LONG: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
782 dst = call(dst, (char *)m68k_write_long_highfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
783 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
784 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
785 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
786 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
787 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
788 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
789 } else { |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
790 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
791 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
792 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
794 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
795 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
796 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
797 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
798 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
799 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
800 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
801 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
802 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
803 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
804 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
805 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
806 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
807 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
808 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
809 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
810 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
811 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
812 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
813 dst = setcc_r(dst, CC_S, FLAG_N); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
814 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
815 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
816 case OPSIZE_BYTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
817 dst = call(dst, (char *)m68k_write_byte); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
818 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
819 case OPSIZE_WORD: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
820 dst = call(dst, (char *)m68k_write_word); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
821 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
822 case OPSIZE_LONG: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
823 dst = call(dst, (char *)m68k_write_long_highfirst); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
824 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
825 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
826 break; |
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
827 case MODE_AREG_INDEX_DISP8: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
828 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
829 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
830 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
831 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
832 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
833 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
834 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
835 if (inst->src.params.regs.sec & 1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
836 if (inst->src.params.regs.sec & 0x10) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
837 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
838 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
839 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
840 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
841 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
842 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
843 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
844 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
845 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
846 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
847 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
848 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
849 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
850 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
851 dst = push_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
852 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
853 if (inst->src.params.regs.sec & 0x10) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
854 if (opts->aregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
855 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
856 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
857 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
858 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
859 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
860 if (opts->dregs[sec_reg] >= 0) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
861 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
862 } else { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
863 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
864 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
865 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
866 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
867 if (src.base == SCRATCH1) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
868 dst = pop_r(dst, SCRATCH1); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
869 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
870 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
871 if (inst->src.params.regs.displacement) { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
872 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
873 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
874 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
875 dst = setcc_r(dst, CC_Z, FLAG_Z); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
876 dst = setcc_r(dst, CC_S, FLAG_N); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
877 switch (inst->extra.size) |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
878 { |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
879 case OPSIZE_BYTE: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
880 dst = call(dst, (char *)m68k_write_byte); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
881 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
882 case OPSIZE_WORD: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
883 dst = call(dst, (char *)m68k_write_word); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
884 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
885 case OPSIZE_LONG: |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
886 dst = call(dst, (char *)m68k_write_long_highfirst); |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
887 break; |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
888 } |
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
889 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
890 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
891 dst = cycles(dst, BUS); |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
892 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
893 if (src.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
894 if (src.base != SCRATCH1) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
895 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
896 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
897 } else if (src.mode == MODE_REG_DISPLACE8) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
898 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
899 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
900 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
901 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
902 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
903 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
904 dst = setcc_r(dst, CC_S, FLAG_N); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
905 switch (inst->extra.size) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
906 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
907 case OPSIZE_BYTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
908 dst = call(dst, (char *)m68k_write_byte); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
909 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
910 case OPSIZE_WORD: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
911 dst = call(dst, (char *)m68k_write_word); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
912 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
913 case OPSIZE_LONG: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
914 dst = call(dst, (char *)m68k_write_long_highfirst); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
915 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
916 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
917 break; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
918 case MODE_ABSOLUTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
919 case MODE_ABSOLUTE_SHORT: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
920 if (src.mode == MODE_REG_DIRECT) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
921 if (src.base != SCRATCH1) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
922 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
923 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
924 } else if (src.mode == MODE_REG_DISPLACE8) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
925 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
926 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
927 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
928 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
929 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
930 dst = cycles(dst, BUS*2); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
931 } else { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
932 dst = cycles(dst, BUS); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
933 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
934 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
935 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
936 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
937 dst = setcc_r(dst, CC_S, FLAG_N); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
938 switch (inst->extra.size) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
939 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
940 case OPSIZE_BYTE: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
941 dst = call(dst, (char *)m68k_write_byte); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
942 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
943 case OPSIZE_WORD: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
944 dst = call(dst, (char *)m68k_write_word); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
945 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
946 case OPSIZE_LONG: |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
947 dst = call(dst, (char *)m68k_write_long_highfirst); |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
948 break; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
949 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
950 break; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
951 default: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
952 printf("address mode %d not implemented (move dst)\n", inst->dst.addr_mode); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
953 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
955 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
956 //add cycles for prefetch |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
957 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
958 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
959 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
960 |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
961 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
962 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
963 int8_t bit,reg; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
964 uint8_t early_cycles; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
965 if(inst->src.addr_mode == MODE_REG) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
966 //reg to mem |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
967 early_cycles = 8; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
968 int8_t dir; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
969 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
970 reg = 15; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
971 dir = -1; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
972 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
973 reg = 0; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
974 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
975 switch (inst->dst.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
976 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
977 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
978 case MODE_AREG_PREDEC: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
979 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
980 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
981 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
982 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
983 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
984 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
985 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
986 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
987 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
988 early_cycles += 4; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
989 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
990 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
991 default: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
992 printf("address mode %d not implemented (movem dst)\n", inst->dst.addr_mode); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
993 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
994 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
995 dst = cycles(dst, early_cycles); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
996 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
997 if (inst->src.params.immed & (1 << bit)) { |
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998 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
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999 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
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1000 } |
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1001 dst = push_r(dst, SCRATCH2); |
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1002 if (reg > 7) { |
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1003 if (opts->aregs[reg-8] >= 0) { |
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1004 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size); |
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1005 } else { |
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1006 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size); |
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1007 } |
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1008 } else { |
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1009 if (opts->dregs[reg] >= 0) { |
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1010 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size); |
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1011 } else { |
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1012 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size); |
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1013 } |
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1014 } |
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1015 if (inst->extra.size == OPSIZE_LONG) { |
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1016 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst); |
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1017 } else { |
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1018 dst = call(dst, (uint8_t *)m68k_write_word); |
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1019 } |
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1020 dst = pop_r(dst, SCRATCH2); |
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1021 if (inst->dst.addr_mode != MODE_AREG_PREDEC) { |
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1022 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
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1023 } |
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1024 } |
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1025 } |
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1026 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
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1027 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
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1028 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
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1029 } else { |
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1030 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
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1031 } |
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1032 } |
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1033 } else { |
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1034 //mem to reg |
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1035 early_cycles = 4; |
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1036 switch (inst->src.addr_mode) |
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1037 { |
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1038 case MODE_AREG_INDIRECT: |
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1039 case MODE_AREG_POSTINC: |
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1040 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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1041 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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1042 } else { |
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1043 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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1044 } |
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1045 break; |
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1046 case MODE_ABSOLUTE: |
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1047 early_cycles += 4; |
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1048 case MODE_ABSOLUTE_SHORT: |
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1049 early_cycles += 4; |
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1050 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
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1051 break; |
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|
1052 default: |
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1053 printf("address mode %d not implemented (movem src)\n", inst->src.addr_mode); |
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1054 exit(1); |
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1055 } |
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1056 dst = cycles(dst, early_cycles); |
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1057 for(reg = 0; reg < 16; reg ++) { |
74
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1058 if (inst->dst.params.immed & (1 << reg)) { |
71
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1059 dst = push_r(dst, SCRATCH1); |
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1060 if (inst->extra.size == OPSIZE_LONG) { |
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1061 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
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1062 } else { |
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1063 dst = call(dst, (uint8_t *)m68k_read_word_scratch1); |
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1064 } |
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1065 if (reg > 7) { |
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1066 if (opts->aregs[reg-8] >= 0) { |
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1067 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size); |
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1068 } else { |
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1069 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size); |
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1070 } |
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1071 } else { |
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1072 if (opts->dregs[reg] >= 0) { |
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1073 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size); |
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1074 } else { |
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1075 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size); |
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1076 } |
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1077 } |
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1078 dst = pop_r(dst, SCRATCH1); |
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1079 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D); |
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1080 } |
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1081 } |
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1082 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
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1083 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
74
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|
1084 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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1085 } else { |
74
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1086 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
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1087 } |
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1088 } |
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1089 } |
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1090 //prefetch |
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1091 dst = cycles(dst, 4); |
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1092 return dst; |
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1093 } |
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1094 |
52
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|
1095 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
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|
1096 { |
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|
1097 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
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1098 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
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1099 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
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1100 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
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1101 int8_t reg = native_reg(&(inst->dst), opts); |
52
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|
1102 if (reg >= 0) { |
64
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61
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|
1103 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
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1104 return xor_rr(dst, reg, reg, inst->extra.size); |
52
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1105 } |
92
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|
1106 x86_ea dst_op; |
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|
1107 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); |
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|
1108 if (dst_op.mode == MODE_REG_DIRECT) { |
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1109 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size); |
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|
1110 } else { |
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|
1111 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
52
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1112 } |
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1113 dst = m68k_save_result(inst, dst, opts); |
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1114 return dst; |
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Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1115 } |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1116 |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1117 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1118 { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1119 x86_ea dst_op; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1120 uint8_t dst_size = inst->extra.size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1121 inst->extra.size--; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1122 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1123 if (dst_op.mode == MODE_REG_DIRECT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1124 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1125 dst = cmp_ir(dst, 0, dst_op.base, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1126 } else { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1127 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1128 dst = cmp_ir(dst, 0, SCRATCH1, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1129 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1130 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1131 inst->extra.size = dst_size; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1132 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1133 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1134 dst = setcc_r(dst, CC_Z, FLAG_Z); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1135 dst = setcc_r(dst, CC_S, FLAG_N); |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1136 //M68K EXT only operates on registers so no need for a call to save result here |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1137 return dst; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1138 } |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1139 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1140 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1141 { |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1142 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1143 switch(inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1144 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1145 case MODE_AREG_INDIRECT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1146 dst = cycles(dst, BUS); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1147 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1148 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1149 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1150 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1151 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1152 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1153 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1154 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1155 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1156 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1157 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1158 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1159 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1160 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1161 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1162 case MODE_AREG_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1163 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1164 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1165 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1166 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1167 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1168 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1169 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1170 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1171 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1172 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1173 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1174 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1175 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1176 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1177 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1178 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1179 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1180 break; |
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1181 case MODE_AREG_INDEX_DISP8: |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1182 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1183 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1184 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1185 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1186 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1187 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1188 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1189 if (inst->src.params.regs.sec & 1) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1190 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1191 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1192 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1193 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1194 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1195 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1196 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1197 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1198 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1199 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1200 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1201 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1202 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1203 } else { |
45cd7d3e7918
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Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1204 if (inst->src.params.regs.sec & 0x10) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1205 if (opts->aregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1206 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1207 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1208 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1209 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1210 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1211 if (opts->dregs[sec_reg] >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1212 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1213 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1214 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1215 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1216 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1217 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1218 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1219 if (inst->src.params.regs.displacement) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1220 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1221 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1222 if (dst_reg >= 0) { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1223 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1224 } else { |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1225 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1226 } |
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1227 break; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1228 case MODE_PC_DISPLACE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1229 dst = cycles(dst, 8); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1230 if (dst_reg >= 0) { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1231 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1232 } else { |
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1233 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1234 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1235 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1236 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1237 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1238 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1239 if (dst_reg >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1240 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1241 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1242 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1243 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1244 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1245 default: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1246 printf("address mode %d not implemented (lea src)\n", inst->src.addr_mode); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1247 exit(1); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1248 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1249 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1250 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1251 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1252 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1253 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1254 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1255 uint32_t after = inst->address + 2; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1256 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1257 dst = cycles(dst, 10); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1258 dst = mov_ir(dst, after, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1259 dst = push_r(dst, SCRATCH1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1260 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1261 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1262 dst = call(dst, (char *)m68k_write_long_highfirst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1263 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1264 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1265 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1266 //dummy address to be replaced later |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1267 dest_addr = dst + 5; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1268 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1269 dst = call(dst, (char *)dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1270 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1271 dst = pop_r(dst, SCRATCH1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1272 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1273 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1274 |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1275 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1276 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1277 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1278 int32_t disp = inst->src.params.immed; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1279 uint32_t after = inst->address + 2; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1280 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1281 if (inst->extra.cond == COND_TRUE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1282 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1283 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1284 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1285 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1286 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1287 dst = jmp(dst, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1288 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1289 uint8_t cond = CC_NZ; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1290 switch (inst->extra.cond) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1291 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1292 case COND_HIGH: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1293 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1294 case COND_LOW_SAME: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1295 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1296 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1297 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1298 case COND_CARRY_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1299 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1300 case COND_CARRY_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1301 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1302 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1303 case COND_NOT_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1304 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1305 case COND_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1306 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1307 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1308 case COND_OVERF_CLR: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1309 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1310 case COND_OVERF_SET: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1311 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1312 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1313 case COND_PLUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1314 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1315 case COND_MINUS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1316 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1317 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1318 case COND_GREATER_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1319 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1320 case COND_LESS: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1321 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1322 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1323 case COND_GREATER: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1324 cond = CC_Z; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1325 case COND_LESS_EQ: |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1326 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1327 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1328 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1329 break; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1330 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1331 if (!dest_addr) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1332 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1333 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1334 dest_addr = dst + 256; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1335 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1336 dst = jcc(dst, cond, dest_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1337 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1338 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1339 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1340 |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1341 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1342 { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1343 uint8_t * dest_addr; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1344 switch(inst->src.addr_mode) |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1345 { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1346 case MODE_AREG_INDIRECT: |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1347 dst = cycles(dst, BUS*2); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1348 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1349 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1350 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1351 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1352 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1353 dst = call(dst, (uint8_t *)m68k_native_addr); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1354 dst = jmp_r(dst, SCRATCH1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1355 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1356 case MODE_PC_DISPLACE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1357 dst = cycles(dst, 10); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1358 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1359 if (!dest_addr) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1360 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1361 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1362 dest_addr = dst + 256; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1363 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1364 dst = jmp(dst, dest_addr); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1365 break; |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1366 case MODE_ABSOLUTE: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1367 case MODE_ABSOLUTE_SHORT: |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1368 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1369 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1370 if (!dest_addr) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1371 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1372 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1373 dest_addr = dst + 256; |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1374 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1375 dst = jmp(dst, dest_addr); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1376 break; |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1377 default: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1378 printf("address mode %d not yet supported (jmp)\n", inst->src.addr_mode); |
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
102
diff
changeset
|
1379 exit(1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1380 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1381 return dst; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1382 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1383 |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1384 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1385 { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1386 uint8_t * dest_addr; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1387 uint32_t after; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1388 switch(inst->src.addr_mode) |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1389 { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1390 case MODE_AREG_INDIRECT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1391 dst = cycles(dst, BUS*2); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1392 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1393 dst = push_r(dst, SCRATCH1); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1394 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1395 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1396 dst = call(dst, (char *)m68k_write_long_highfirst); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1397 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1398 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1399 } else { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1400 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1401 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1402 dst = call(dst, (uint8_t *)m68k_native_addr); |
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1403 dst = call_r(dst, SCRATCH1); |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1404 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
1405 dst = pop_r(dst, SCRATCH1); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1406 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1407 case MODE_PC_DISPLACE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1408 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1409 dst = cycles(dst, 10); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1410 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1411 dst = push_r(dst, SCRATCH1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1412 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1413 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1414 dst = call(dst, (char *)m68k_write_long_highfirst); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1415 dest_addr = get_native_address(opts->native_code_map, inst->src.params.regs.displacement + inst->address + 2); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1416 if (!dest_addr) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1417 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1418 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1419 dest_addr = dst + 5; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1420 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1421 dst = call(dst, (char *)dest_addr); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1422 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1423 dst = pop_r(dst, SCRATCH1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1424 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1425 case MODE_ABSOLUTE: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1426 case MODE_ABSOLUTE_SHORT: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1427 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1428 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1429 dst = mov_ir(dst, inst->address + 8, SCRATCH1, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1430 dst = push_r(dst, SCRATCH1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1431 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1432 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1433 dst = call(dst, (char *)m68k_write_long_highfirst); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1434 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1435 if (!dest_addr) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1436 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1437 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1438 dest_addr = dst + 5; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1439 } |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1440 dst = call(dst, (char *)dest_addr); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1441 //would add_ir(dst, 8, RSP, SZ_Q) be faster here? |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1442 dst = pop_r(dst, SCRATCH1); |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1443 break; |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1444 default: |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1445 printf("address mode %d not yet supported (jsr)\n", inst->src.addr_mode); |
105 | 1446 exit(1); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1447 } |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1448 return dst; |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1449 } |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1450 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1451 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1452 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1453 //TODO: Add cycles |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1454 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1455 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1456 dst = call(dst, (char *)m68k_read_long_scratch1); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1457 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1458 dst = jcc(dst, CC_NZ, dst+3); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1459 dst = retn(dst); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1460 dst = jmp(dst, (char *)m68k_modified_ret_addr); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1461 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1462 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1463 |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1464 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1465 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1466 //best case duration |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1467 dst = cycles(dst, 10); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1468 uint8_t * skip_loc = NULL; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1469 //TODO: Check if COND_TRUE technically valid here even though |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1470 //it's basically a slow NOP |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1471 if (inst->extra.cond != COND_FALSE) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1472 uint8_t cond = CC_NZ; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1473 switch (inst->extra.cond) |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1474 { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1475 case COND_HIGH: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1476 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1477 case COND_LOW_SAME: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1478 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1479 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1480 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1481 case COND_CARRY_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1482 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1483 case COND_CARRY_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1484 dst = cmp_ir(dst, 0, FLAG_C, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1485 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1486 case COND_NOT_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1487 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1488 case COND_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1489 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1490 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1491 case COND_OVERF_CLR: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1492 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1493 case COND_OVERF_SET: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1494 dst = cmp_ir(dst, 0, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1495 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1496 case COND_PLUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1497 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1498 case COND_MINUS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1499 dst = cmp_ir(dst, 0, FLAG_N, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1500 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1501 case COND_GREATER_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1502 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1503 case COND_LESS: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1504 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1505 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1506 case COND_GREATER: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1507 cond = CC_Z; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1508 case COND_LESS_EQ: |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1509 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1510 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1511 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1512 break; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1513 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1514 skip_loc = dst + 1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1515 dst = jcc(dst, cond, dst + 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1516 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1517 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1518 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1519 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1520 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1521 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1522 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1523 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1524 uint8_t *loop_end_loc = dst+1; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1525 dst = jcc(dst, CC_Z, dst+2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1526 uint32_t after = inst->address + 2; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1527 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1528 if (!dest_addr) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1529 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1530 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1531 dest_addr = dst + 256; |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1532 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1533 dst = jmp(dst, dest_addr); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1534 *loop_end_loc = dst - (loop_end_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1535 if (skip_loc) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1536 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1537 *skip_loc = dst - (skip_loc+1); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1538 dst = cycles(dst, 2); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1539 } else { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1540 dst = cycles(dst, 4); |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1541 } |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1542 return dst; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1543 } |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1544 |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1545 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1546 { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1547 int8_t reg = native_reg(&(inst->src), opts); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1548 //compensate for displacement word |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1549 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1550 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1551 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1552 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1553 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1554 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1555 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1556 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1557 dst = call(dst, (char *)m68k_write_long_highfirst); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1558 if (reg >= 0) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1559 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1560 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1561 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1562 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1563 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1564 //prefetch |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1565 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1566 return dst; |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1567 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1568 |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1569 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1570 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1571 typedef uint8_t * (*shift_clr_t)(uint8_t * out, uint8_t dst, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1572 typedef uint8_t * (*shift_clrdisp8_t)(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1573 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1574 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1575 { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1576 uint8_t * end_off = NULL; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1577 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1578 dst = cycles(dst, BUS); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1579 //Memory shift |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1580 dst = shift_ir(dst, 1, dst_op->base, SZ_W); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1581 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1582 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1583 if (src_op->mode == MODE_IMMED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1584 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1585 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1586 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1587 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1588 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1589 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1590 if (src_op->base != RCX) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1591 if (src_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1592 dst = mov_rr(dst, src_op->base, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1593 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1594 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1595 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1596 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1597 dst = and_ir(dst, 63, RCX, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1598 //add 2 cycles for every bit shifted |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1599 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1600 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1601 //x86 shifts modulo 32 for operand sizes less than 64-bits |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1602 //but M68K shifts modulo 64, so we need to check for large shifts here |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1603 dst = cmp_ir(dst, 32, RCX, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1604 uint8_t * norm_shift_off = dst + 1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1605 dst = jcc(dst, CC_L, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1606 if (special) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1607 if (inst->extra.size == OPSIZE_LONG) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1608 uint8_t * neq_32_off = dst + 1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1609 dst = jcc(dst, CC_NZ, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1610 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1611 //set the carry bit to the lsb |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1612 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1613 dst = special(dst, 1, dst_op->base, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1614 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1615 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1616 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1617 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1618 dst = jmp(dst, dst+4); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1619 *neq_32_off = dst - (neq_32_off+1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1620 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1621 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1622 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1623 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1624 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1625 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1626 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1627 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1628 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1629 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1630 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1631 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1632 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1633 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1634 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1635 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1636 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1637 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1638 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1639 end_off = dst+1; |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1640 dst = jmp(dst, dst+2); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1641 *norm_shift_off = dst - (norm_shift_off+1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1642 if (dst_op->mode == MODE_REG_DIRECT) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1643 dst = shift_clr(dst, dst_op->base, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1644 } else { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1645 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1646 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1647 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1648 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1649 |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1650 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1651 if (!special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1652 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1653 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1654 dst = setcc_r(dst, CC_C, FLAG_C); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1655 dst = setcc_r(dst, CC_Z, FLAG_Z); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1656 dst = setcc_r(dst, CC_S, FLAG_N); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1657 if (special && end_off) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1658 *end_off = dst - (end_off + 1); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1659 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1660 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1661 //set X flag to same as C flag |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1662 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1663 if (inst->src.addr_mode == MODE_UNUSED) { |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1664 dst = m68k_save_result(inst, dst, opts); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1665 } |
66 | 1666 return dst; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1667 } |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1668 |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1669 #define BIT_SUPERVISOR 5 |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1670 |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1671 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1672 { |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1673 uint8_t * end_off; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1674 map_native_address(opts->native_code_map, inst->address, dst); |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
1675 dst = check_cycles_int(dst, inst->address); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1676 if (inst->op == M68K_MOVE) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1677 return translate_m68k_move(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1678 } else if(inst->op == M68K_LEA) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1679 return translate_m68k_lea(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1680 } else if(inst->op == M68K_BSR) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1681 return translate_m68k_bsr(dst, inst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1682 } else if(inst->op == M68K_BCC) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1683 return translate_m68k_bcc(dst, inst, opts); |
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1684 } else if(inst->op == M68K_JMP) { |
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
1685 return translate_m68k_jmp(dst, inst, opts); |
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1686 } else if(inst->op == M68K_JSR) { |
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1687 return translate_m68k_jsr(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1688 } else if(inst->op == M68K_RTS) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1689 return translate_m68k_rts(dst, inst, opts); |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1690 } else if(inst->op == M68K_DBCC) { |
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1691 return translate_m68k_dbcc(dst, inst, opts); |
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1692 } else if(inst->op == M68K_CLR) { |
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1693 return translate_m68k_clr(dst, inst, opts); |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1694 } else if(inst->op == M68K_MOVEM) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1695 return translate_m68k_movem(dst, inst, opts); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1696 } else if(inst->op == M68K_LINK) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
1697 return translate_m68k_link(dst, inst, opts); |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1698 } else if(inst->op == M68K_EXT) { |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1699 return translate_m68k_ext(dst, inst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1700 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1701 x86_ea src_op, dst_op; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1702 if (inst->src.addr_mode != MODE_UNUSED) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1703 dst = translate_m68k_src(inst, &src_op, dst, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1704 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1705 if (inst->dst.addr_mode != MODE_UNUSED) { |
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1706 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1707 } |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1708 switch(inst->op) |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1709 { |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1710 //case M68K_ABCD: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1711 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1712 case M68K_ADD: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1713 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1714 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1715 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1716 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1717 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1718 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1719 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1720 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1721 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1722 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1723 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1724 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1725 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1726 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1727 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1728 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1729 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1730 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1731 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1732 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1733 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1734 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1735 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1736 //case M68K_ADDX: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1737 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1738 case M68K_AND: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1739 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1740 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1741 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1742 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1743 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1744 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1745 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1746 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1747 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1748 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1749 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1750 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1751 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1752 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1753 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1754 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1755 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1756 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1757 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1758 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1759 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1760 break; |
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1761 case M68K_ANDI_CCR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1762 case M68K_ANDI_SR: |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1763 dst = cycles(dst, 20); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1764 //TODO: If ANDI to SR, trap if not in supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1765 if (!(inst->src.params.immed & 0x1)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1766 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1767 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1768 if (!(inst->src.params.immed & 0x2)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1769 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1770 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1771 if (!(inst->src.params.immed & 0x4)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1772 dst = mov_ir(dst, 0, FLAG_Z, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1773 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1774 if (!(inst->src.params.immed & 0x8)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1775 dst = mov_ir(dst, 0, FLAG_N, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1776 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1777 if (!(inst->src.params.immed & 0x10)) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1778 dst = mov_irind(dst, 0, CONTEXT, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1779 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1780 if (inst->op == M68K_ANDI_SR) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1781 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1782 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1783 //leave supervisor mode |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1784 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1785 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1786 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B); |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1787 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1788 } |
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
1789 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1790 case M68K_ASL: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1791 case M68K_LSL: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1792 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1793 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1794 case M68K_ASR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1795 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1796 break; |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1797 case M68K_LSR: |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1798 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); |
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
1799 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1800 /*case M68K_BCHG: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1801 case M68K_BCLR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1802 case M68K_BSET: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1803 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1804 case M68K_BTST: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1805 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6); |
67 | 1806 if (src_op.mode == MODE_IMMED) { |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1807 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1808 src_op.disp &= 0x7; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1809 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1810 if (dst_op.mode == MODE_REG_DIRECT) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1811 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1812 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1813 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1814 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1815 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1816 if (src_op.mode == MODE_REG_DISPLACE8) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1817 if (dst_op.base == SCRATCH1) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1818 dst = push_r(dst, SCRATCH2); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1819 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1820 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1821 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1822 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1823 src_op.base = SCRATCH1; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1824 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1825 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1826 if (inst->extra.size == OPSIZE_BYTE) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1827 dst = and_ir(dst, 0x7, src_op.base, SZ_B); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1828 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1829 if (dst_op.mode == MODE_REG_DIRECT) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1830 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1831 } else { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1832 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1833 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1834 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1835 //x86 sets the carry flag to the value of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1836 //68K sets the zero flag to the complement of the bit tested |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1837 dst = setcc_r(dst, CC_NC, FLAG_Z); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1838 if (src_op.base == SCRATCH2) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1839 dst = pop_r(dst, SCRATCH2); |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1840 } |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
1841 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1842 /*case M68K_CHK: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1843 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1844 case M68K_CMP: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1845 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1846 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1847 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1848 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1849 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1850 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1851 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1852 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1853 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1854 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1855 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1856 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1857 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1858 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1859 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1860 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1861 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1862 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1863 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1864 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1865 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1866 /*case M68K_DIVS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1867 case M68K_DIVU: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1868 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1869 case M68K_EOR: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1870 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1871 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1872 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1873 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1874 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1875 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1876 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1877 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1878 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1879 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1880 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1881 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1882 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1883 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1884 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1885 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1886 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1887 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1888 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1889 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1890 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1891 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1892 /*case M68K_EORI_CCR: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
1893 case M68K_EORI_SR:*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1894 case M68K_EXG: |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1895 dst = cycles(dst, 6); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1896 if (dst_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1897 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1898 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1899 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1900 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1901 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1902 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1903 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1904 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1905 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1906 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1907 if (src_op.mode == MODE_REG_DIRECT) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1908 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1909 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1910 } else { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1911 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1912 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1913 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1914 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1915 } |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1916 break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1917 case M68K_ILLEGAL: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1918 dst = call(dst, (uint8_t *)m68k_save_context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1919 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1920 dst = call(dst, (uint8_t *)print_regs_exit); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1921 break; |
105 | 1922 case M68K_MOVE_FROM_SR: |
1923 //TODO: Trap if not in system mode | |
1924 dst = call(dst, (uint8_t *)get_sr); | |
1925 if (dst_op.mode == MODE_REG_DIRECT) { | |
1926 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W); | |
1927 } else { | |
1928 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W); | |
1929 } | |
1930 dst = m68k_save_result(inst, dst, opts); | |
1931 break; | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1932 case M68K_MOVE_CCR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1933 case M68K_MOVE_SR: |
71
f80fa1776507
Implement more instructions and address modes
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parents:
70
diff
changeset
|
1934 //TODO: Privilege check for MOVE to SR |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1935 if (src_op.mode == MODE_IMMED) { |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1936 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1937 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B); |
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1938 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B); |
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Implement more instructions and address modes
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1939 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B); |
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1940 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B); |
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1941 if (inst->op == M68K_MOVE_SR) { |
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1942 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
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1943 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
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1944 //leave supervisor mode |
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1945 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
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1946 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
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1947 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
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1948 } |
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1949 } |
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1950 dst = cycles(dst, 12); |
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1951 } else { |
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1952 if (src_op.base != SCRATCH1) { |
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1953 if (src_op.mode == MODE_REG_DIRECT) { |
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1954 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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1955 } else { |
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1956 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W); |
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1957 } |
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1958 } |
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1959 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr)); |
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1960 dst = cycles(dst, 12); |
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1961 |
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1962 } |
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1963 break; |
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1964 case M68K_MOVE_USP: |
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1965 dst = cycles(dst, BUS); |
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1966 //TODO: Trap if not in supervisor mode |
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1967 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B); |
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1968 if (inst->src.addr_mode == MODE_UNUSED) { |
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1969 if (dst_op.mode == MODE_REG_DIRECT) { |
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1970 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D); |
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1971 } else { |
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1972 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D); |
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1973 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
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1974 } |
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1975 } else { |
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1976 if (src_op.mode == MODE_REG_DIRECT) { |
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1977 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
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1978 } else { |
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1979 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
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1980 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
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1981 } |
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1982 } |
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1983 break; |
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1984 /*case M68K_MOVEP: |
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1985 case M68K_MULS: |
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1986 case M68K_MULU: |
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1987 case M68K_NBCD:*/ |
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1988 case M68K_NEG: |
82
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1989 if (dst_op.mode == MODE_REG_DIRECT) { |
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1990 dst = neg_r(dst, dst_op.base, inst->extra.size); |
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1991 } else { |
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1992 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
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1993 } |
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1994 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
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1995 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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1996 dst = setcc_r(dst, CC_S, FLAG_N); |
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1997 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
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1998 dst = m68k_save_result(inst, dst, opts); |
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1999 break; |
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2000 /*case M68K_NEGX: |
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2001 break;*/ |
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2002 case M68K_NOP: |
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2003 dst = cycles(dst, BUS); |
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2004 break; |
82
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2005 case M68K_NOT: |
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2006 if (dst_op.mode == MODE_REG_DIRECT) { |
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2007 dst = not_r(dst, dst_op.base, inst->extra.size); |
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|
2008 } else { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
2009 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
6331ddec228f
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|
2010 } |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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|
2011 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
6331ddec228f
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|
2012 dst = setcc_r(dst, CC_Z, FLAG_Z); |
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|
2013 dst = setcc_r(dst, CC_S, FLAG_N); |
6331ddec228f
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|
2014 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
6331ddec228f
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|
2015 dst = m68k_save_result(inst, dst, opts); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
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81
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|
2016 break; |
14
2bdad0f52f42
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diff
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|
2017 case M68K_OR: |
49
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|
2018 dst = cycles(dst, BUS); |
d2e43d64e999
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|
2019 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
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46
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|
2020 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
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46
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|
2021 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
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46
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|
2022 } else { |
d2e43d64e999
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|
2023 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
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46
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|
2024 } |
d2e43d64e999
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46
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|
2025 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
d2e43d64e999
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46
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|
2026 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
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parents:
46
diff
changeset
|
2027 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
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46
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|
2028 if (dst_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
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46
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|
2029 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
d2e43d64e999
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46
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|
2030 } else { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
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|
2031 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
d2e43d64e999
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46
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|
2032 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2033 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2034 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2035 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2036 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2037 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2038 dst = m68k_save_result(inst, dst, opts); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2039 break; |
106 | 2040 case M68K_ORI_CCR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2041 case M68K_ORI_SR: |
106 | 2042 dst = cycles(dst, 20); |
2043 //TODO: If ANDI to SR, trap if not in supervisor mode | |
2044 if (inst->src.params.immed & 0x1) { | |
2045 dst = mov_ir(dst, 1, FLAG_C, SZ_B); | |
2046 } | |
2047 if (inst->src.params.immed & 0x2) { | |
2048 dst = mov_ir(dst, 1, FLAG_V, SZ_B); | |
2049 } | |
2050 if (inst->src.params.immed & 0x4) { | |
2051 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); | |
2052 } | |
2053 if (inst->src.params.immed & 0x8) { | |
2054 dst = mov_ir(dst, 1, FLAG_N, SZ_B); | |
2055 } | |
2056 if (inst->src.params.immed & 0x10) { | |
2057 dst = mov_irind(dst, 1, CONTEXT, SZ_B); | |
2058 } | |
2059 if (inst->op == M68K_ANDI_SR) { | |
2060 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); | |
2061 } | |
2062 break; | |
2063 /*case M68K_PEA: | |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2064 case M68K_RESET: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2065 case M68K_ROL: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2066 case M68K_ROR: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2067 case M68K_ROXL: |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2068 case M68K_ROXR:*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2069 case M68K_RTE: |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2070 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2071 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2072 dst = push_r(dst, SCRATCH1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2073 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2074 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2075 dst = call(dst, (uint8_t *)m68k_read_word_scratch1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2076 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2077 dst = call(dst, (uint8_t *)set_sr); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2078 dst = pop_r(dst, SCRATCH1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2079 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2080 end_off = dst+1; |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2081 dst = jcc(dst, CC_NC, dst+2); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2082 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2083 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2084 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2085 *end_off = dst - (end_off+1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2086 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2087 dst = jmp_r(dst, SCRATCH1); |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2088 break; |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2089 /*case M68K_RTR: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2090 case M68K_SBCD: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2091 case M68K_SCC: |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2092 case M68K_STOP: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2093 break;*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2094 case M68K_SUB: |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2095 dst = cycles(dst, BUS); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2096 if (src_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2097 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2098 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2099 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2100 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2101 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2102 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2103 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2104 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2105 if (dst_op.mode == MODE_REG_DIRECT) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2106 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2107 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2108 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2109 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2110 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2111 dst = setcc_r(dst, CC_C, FLAG_C); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2112 dst = setcc_r(dst, CC_Z, FLAG_Z); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2113 dst = setcc_r(dst, CC_S, FLAG_N); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2114 dst = setcc_r(dst, CC_O, FLAG_V); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2115 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2116 dst = m68k_save_result(inst, dst, opts); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2117 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2118 //case M68K_SUBX: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2119 // break; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2120 case M68K_SWAP: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2121 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2122 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2123 dst = rol_ir(dst, 16, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2124 } else{ |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2125 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2126 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2127 dst = mov_ir(dst, 0, FLAG_C, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2128 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2129 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2130 dst = mov_ir(dst, 0, FLAG_V, SZ_B); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2131 break; |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2132 /*case M68K_TAS: |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2133 case M68K_TRAP: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2134 case M68K_TRAPV:*/ |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2135 case M68K_TST: |
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2136 dst = cycles(dst, BUS); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2137 if (src_op.mode == MODE_REG_DIRECT) { |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2138 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2139 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2140 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2141 } |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2142 dst = setcc_r(dst, CC_C, FLAG_C); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2143 dst = setcc_r(dst, CC_Z, FLAG_Z); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2144 dst = setcc_r(dst, CC_S, FLAG_N); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2145 dst = setcc_r(dst, CC_O, FLAG_V); |
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2146 break; |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2147 case M68K_UNLK: |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2148 dst = cycles(dst, BUS); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2149 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2150 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2151 } else { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2152 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2153 } |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2154 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2155 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2156 if (dst_op.mode == MODE_REG_DIRECT) { |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2157 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D); |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2158 } else { |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2159 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2160 } |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2161 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2162 break; |
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2163 /*case M68K_INVALID: |
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2164 break;*/ |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2165 default: |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2166 printf("instruction %d not yet implemented\n", inst->op); |
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
2167 exit(1); |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2168 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2169 return dst; |
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2170 } |
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2171 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2172 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context) |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2173 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2174 m68kinst instbuf; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2175 x86_68k_options * opts = context->options; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2176 uint8_t * dst = opts->cur_code; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2177 uint8_t * dst_end = opts->code_end; |
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2178 if(get_native_address(opts->native_code_map, address)) { |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2179 return dst; |
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
2180 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2181 char disbuf[1024]; |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2182 uint16_t *encoded, *next; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2183 if ((address & 0xFFFFFF) < 0x400000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2184 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2185 } else if ((address & 0xFFFFFF) > 0xE00000) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2186 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2187 } else { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2188 printf("attempt to translate non-memory address: %X\n", address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2189 exit(1); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2190 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2191 do { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2192 do { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2193 if (dst_end-dst < 128) { |
102
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2194 if (dst_end-dst < 5) { |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2195 puts("out of code memory, not enough space for jmp to next chunk"); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2196 exit(1); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2197 } |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2198 size_t size = 1024*1024; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2199 opts->cur_code = alloc_code(&size); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2200 opts->code_end = opts->cur_code + size; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2201 jmp(dst, opts->cur_code); |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2202 dst = opts->cur_code; |
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
2203 dst_end = opts->code_end; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2204 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2205 next = m68k_decode(encoded, &instbuf, address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2206 address += (next-encoded)*2; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2207 encoded = next; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2208 m68k_disasm(&instbuf, disbuf); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2209 printf("%X: %s\n", instbuf.address, disbuf); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2210 dst = translate_m68k(dst, &instbuf, opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2211 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2212 process_deferred(opts); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2213 if (opts->deferred) { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2214 address = opts->deferred->address; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2215 encoded = context->mem_pointers[0] + address/2; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2216 } else { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2217 encoded = NULL; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2218 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2219 } while(encoded != NULL); |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2220 opts->cur_code = dst; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2221 return dst; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2222 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2223 |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2224 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address) |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2225 { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2226 address &= 0xFFFFFF; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2227 uint8_t * ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2228 if (!ret) { |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2229 translate_m68k_stream(address, context); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2230 ret = get_native_address(context->native_code_map, address); |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2231 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2232 return ret; |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2233 } |
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
2234 |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2235 void start_68k_context(m68k_context * context, uint32_t address) |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2236 { |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2237 uint8_t * addr = get_native_address(context->native_code_map, address); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2238 m68k_start_context(addr, context); |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2239 } |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2240 |
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
2241 void m68k_reset(m68k_context * context) |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
2242 { |
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2243 //TODO: Make this actually use the normal read functions |
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2244 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1]; |
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2245 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3]; |
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2246 start_68k_context(context, address); |
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2247 } |
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2248 |
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2249 void init_x86_68k_opts(x86_68k_options * opts) |
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2250 { |
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2251 opts->flags = 0; |
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2252 for (int i = 0; i < 8; i++) |
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2253 opts->dregs[i] = opts->aregs[i] = -1; |
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2254 opts->dregs[0] = R10; |
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2255 opts->dregs[1] = R11; |
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2256 opts->dregs[2] = R12; |
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2257 opts->aregs[0] = R13; |
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2258 opts->aregs[1] = R14; |
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2259 opts->aregs[7] = R15; |
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2260 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
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2261 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
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2262 opts->deferred = NULL; |
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2263 size_t size = 1024 * 1024; |
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2264 opts->cur_code = alloc_code(&size); |
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2265 opts->code_end = opts->cur_code + size; |
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2266 } |
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2267 |
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2268 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) |
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2269 { |
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2270 memset(context, 0, sizeof(m68k_context)); |
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2271 context->native_code_map = native_code_map; |
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2272 context->options = opts; |
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2273 context->int_cycle = 0xFFFFFFFF; |
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2274 } |
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2275 |