Mercurial > repos > blastem
annotate segacd.c @ 2127:1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Sat, 12 Mar 2022 22:54:41 -0800 |
parents | da1fae7d5407 |
children | b0dcf5c9f353 |
rev | line source |
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1502
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Initial skeleton of Sega CD memory handlers
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1 #include <stdlib.h> |
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2 #include <string.h> |
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4 #include "cd_graphics.h" |
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5 #include "genesis.h" |
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6 #include "util.h" |
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7 #include "debug.h" |
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8 #include "gdb_remote.h" |
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Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
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9 #include "blastem.h" |
1502
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10 |
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11 #define SCD_MCLKS 50000000 |
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12 #define SCD_PERIPH_RESET_CLKS (SCD_MCLKS / 10) |
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13 #define TIMER_TICK_CLKS 1536 |
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14 |
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15 enum { |
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16 GA_SUB_CPU_CTRL, |
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17 GA_MEM_MODE, |
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18 GA_CDC_CTRL, |
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19 GA_CDC_REG_DATA, |
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20 GA_CDC_HOST_DATA, |
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21 GA_CDC_DMA_ADDR, |
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22 GA_STOP_WATCH, |
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23 GA_COMM_FLAG, |
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24 GA_COMM_CMD0, |
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25 GA_COMM_CMD1, |
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26 GA_COMM_CMD2, |
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27 GA_COMM_CMD3, |
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28 GA_COMM_CMD4, |
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29 GA_COMM_CMD5, |
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30 GA_COMM_CMD6, |
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31 GA_COMM_CMD7, |
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32 GA_COMM_STATUS0, |
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33 GA_COMM_STATUS1, |
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34 GA_COMM_STATUS2, |
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35 GA_COMM_STATUS3, |
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36 GA_COMM_STATUS4, |
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37 GA_COMM_STATUS5, |
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38 GA_COMM_STATUS6, |
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39 GA_COMM_STATUS7, |
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40 GA_TIMER, |
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41 GA_INT_MASK, |
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42 GA_CDD_FADER, |
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43 GA_CDD_CTRL, |
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44 GA_CDD_STATUS0, |
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45 GA_CDD_STATUS1, |
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46 GA_CDD_STATUS2, |
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47 GA_CDD_STATUS3, |
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48 GA_CDD_STATUS4, |
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49 GA_CDD_CMD0, |
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50 GA_CDD_CMD1, |
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51 GA_CDD_CMD2, |
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52 GA_CDD_CMD3, |
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53 GA_CDD_CMD4, |
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54 GA_FONT_COLOR, |
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55 GA_FONT_BITS, |
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56 GA_FONT_DATA0, |
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57 GA_FONT_DATA1, |
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58 GA_FONT_DATA2, |
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59 GA_FONT_DATA3, |
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60 GA_SUBCODE_START = 0x80, |
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61 GA_SUBCODE_MIRROR = 0xC0, |
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62 |
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63 GA_HINT_VECTOR = GA_CDC_REG_DATA |
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64 }; |
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65 //GA_SUB_CPU_CTRL |
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66 #define BIT_IEN2 0x8000 |
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67 #define BIT_IFL2 0x0100 |
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68 #define BIT_LEDG 0x0200 |
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69 #define BIT_LEDR 0x0100 |
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70 #define BIT_SBRQ 0x0002 |
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71 #define BIT_SRES 0x0001 |
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72 #define BIT_PRES 0x0001 |
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73 //GA_MEM_MODE |
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74 #define MASK_PROG_BANK 0x00C0 |
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75 #define BIT_OVERWRITE 0x0010 |
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76 #define BIT_UNDERWRITE 0x0008 |
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77 #define MASK_PRIORITY (BIT_OVERWRITE|BIT_UNDERWRITE) |
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78 #define BIT_MEM_MODE 0x0004 |
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79 #define BIT_DMNA 0x0002 |
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80 #define BIT_RET 0x0001 |
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81 |
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82 //GA_CDC_CTRL |
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83 #define BIT_EDT 0x8000 |
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84 #define BIT_DSR 0x4000 |
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85 |
2080 | 86 //GA_CDD_CTRL |
87 #define BIT_MUTE 0x0100 | |
88 | |
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89 enum { |
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90 DST_MAIN_CPU = 2, |
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91 DST_SUB_CPU, |
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92 DST_PCM_RAM, |
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93 DST_PROG_RAM, |
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94 DST_WORD_RAM = 7 |
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95 }; |
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96 |
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97 //GA_INT_MASK |
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98 #define BIT_MASK_IEN1 0x0002 |
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99 #define BIT_MASK_IEN2 0x0004 |
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100 #define BIT_MASK_IEN3 0x0008 |
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101 #define BIT_MASK_IEN4 0x0010 |
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102 #define BIT_MASK_IEN5 0x0020 |
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103 #define BIT_MASK_IEN6 0x0040 |
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104 |
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105 //GA_CDD_CTRL |
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106 #define BIT_HOCK 0x0004 |
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107 |
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108 static void *prog_ram_wp_write16(uint32_t address, void *vcontext, uint16_t value) |
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109 { |
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110 m68k_context *m68k = vcontext; |
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111 segacd_context *cd = m68k->system; |
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112 //if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 9) + 8)))) { |
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113 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) { |
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114 cd->prog_ram[address >> 1] = value; |
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115 m68k_invalidate_code_range(m68k, address, address + 2); |
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116 } |
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117 return vcontext; |
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118 } |
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119 |
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120 static void *prog_ram_wp_write8(uint32_t address, void *vcontext, uint8_t value) |
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121 { |
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122 m68k_context *m68k = vcontext; |
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123 segacd_context *cd = m68k->system; |
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124 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) { |
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125 ((uint8_t *)cd->prog_ram)[address ^ 1] = value; |
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126 m68k_invalidate_code_range(m68k, address, address + 1); |
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127 } |
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128 return vcontext; |
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129 } |
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130 |
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131 static uint16_t word_ram_2M_read16(uint32_t address, void *vcontext) |
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132 { |
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133 m68k_context *m68k = vcontext; |
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134 //TODO: fixme for interleaving |
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135 uint16_t* bank = m68k->mem_pointers[1]; |
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136 if (!bank) { |
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137 return 0xFFFF; |
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138 } |
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139 uint16_t raw = bank[address >> 2]; |
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140 if (address & 2) { |
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141 return (raw & 0xF) | (raw << 4 & 0xF00); |
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142 } else { |
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143 return (raw >> 4 & 0xF00) | (raw >> 8 & 0xF); |
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144 } |
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145 } |
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146 |
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147 static uint8_t word_ram_2M_read8(uint32_t address, void *vcontext) |
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148 { |
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149 uint16_t word = word_ram_2M_read16(address, vcontext); |
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150 if (address & 1) { |
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151 return word; |
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152 } |
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153 return word >> 8; |
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154 } |
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155 |
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156 static void *word_ram_2M_write8(uint32_t address, void *vcontext, uint8_t value) |
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157 { |
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158 m68k_context *m68k = vcontext; |
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159 segacd_context *cd = m68k->system; |
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160 value &= 0xF; |
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161 uint16_t priority = cd->gate_array[GA_MEM_MODE] & MASK_PRIORITY; |
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162 |
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163 if (priority == BIT_OVERWRITE && !value) { |
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164 return vcontext; |
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165 } |
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166 if (priority == BIT_UNDERWRITE) { |
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167 if (!value) { |
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168 return vcontext; |
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169 } |
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170 uint8_t old = word_ram_2M_read8(address, vcontext); |
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171 if (old) { |
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172 return vcontext; |
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173 } |
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174 } |
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175 uint16_t* bank = m68k->mem_pointers[1]; |
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176 if (!bank) { |
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177 return vcontext; |
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178 } |
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179 uint16_t raw = bank[address >> 2]; |
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180 uint16_t shift = ((address & 3) * 4); |
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181 raw &= ~(0xF000 >> shift); |
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182 raw |= value << (12 - shift); |
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183 bank[address >> 2] = raw; |
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184 return vcontext; |
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185 } |
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186 |
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187 |
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188 static void *word_ram_2M_write16(uint32_t address, void *vcontext, uint16_t value) |
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189 { |
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190 word_ram_2M_write8(address, vcontext, value >> 8); |
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191 return word_ram_2M_write8(address + 1, vcontext, value); |
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192 } |
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193 |
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194 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext) |
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195 { |
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196 return 0; |
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197 } |
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198 |
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199 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext) |
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200 { |
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201 return 0; |
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202 } |
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203 |
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204 static void *word_ram_1M_write16(uint32_t address, void *vcontext, uint16_t value) |
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205 { |
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206 return vcontext; |
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207 } |
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208 |
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209 static void *word_ram_1M_write8(uint32_t address, void *vcontext, uint8_t value) |
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210 { |
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211 return vcontext; |
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212 } |
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213 |
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214 |
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215 static uint16_t unmapped_prog_read16(uint32_t address, void *vcontext) |
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216 { |
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217 return 0xFFFF; |
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218 } |
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219 |
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220 static uint8_t unmapped_prog_read8(uint32_t address, void *vcontext) |
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221 { |
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222 return 0xFF; |
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223 } |
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224 |
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225 static void *unmapped_prog_write16(uint32_t address, void *vcontext, uint16_t value) |
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226 { |
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227 return vcontext; |
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228 } |
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229 |
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230 static void *unmapped_prog_write8(uint32_t address, void *vcontext, uint8_t value) |
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231 { |
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232 return vcontext; |
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233 } |
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234 |
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235 static uint16_t unmapped_word_read16(uint32_t address, void *vcontext) |
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236 { |
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237 return 0xFFFF; |
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238 } |
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239 |
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240 static uint8_t unmapped_word_read8(uint32_t address, void *vcontext) |
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241 { |
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242 return 0xFF; |
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243 } |
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244 |
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245 static void *unmapped_word_write16(uint32_t address, void *vcontext, uint16_t value) |
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246 { |
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247 return vcontext; |
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248 } |
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249 |
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250 static void *unmapped_word_write8(uint32_t address, void *vcontext, uint8_t value) |
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251 { |
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252 return vcontext; |
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253 } |
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254 |
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255 static uint32_t cell_image_translate_address(uint32_t address) |
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256 { |
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257 uint32_t word_of_cell = address & 2; |
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258 if (address < 0x10000) { |
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259 //64x32 cell view |
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260 uint32_t line_of_column = address & 0x3FC; |
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261 uint32_t column = address & 0xFC00; |
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262 address = (line_of_column << 6) | (column >> 8) | word_of_cell; |
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263 } else if (address < 0x18000) { |
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264 //64x16 cell view |
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265 uint32_t line_of_column = address & 0x1FC; |
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266 uint32_t column = address & 0x7E00; |
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267 address = 0x10000 | (line_of_column << 6) | (column >> 7) | word_of_cell; |
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268 } else if (address < 0x1C000) { |
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269 //64x8 cell view |
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270 uint32_t line_of_column = address & 0x00FC; |
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271 uint32_t column = address & 0x3F00; |
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272 address = 0x18000 | (line_of_column << 6) | (column >> 6) | word_of_cell; |
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273 } else { |
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274 //64x4 cell view |
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275 uint32_t line_of_column = address & 0x007C; |
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276 uint32_t column = address & 0x1F80; |
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277 address &= 0x1E000; |
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278 address |= (line_of_column << 6) | (column >> 5) | word_of_cell; |
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279 } |
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280 return address; |
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281 } |
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282 |
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283 static uint16_t cell_image_read16(uint32_t address, void *vcontext) |
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284 { |
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285 address = cell_image_translate_address(address); |
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286 m68k_context *m68k = vcontext; |
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287 genesis_context *gen = m68k->system; |
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288 segacd_context *cd = gen->expansion; |
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289 if (!m68k->mem_pointers[cd->memptr_start_index + 1]) { |
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290 return 0xFFFF; |
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291 } |
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292 return m68k->mem_pointers[cd->memptr_start_index + 1][address>>1]; |
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293 } |
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294 |
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295 static uint8_t cell_image_read8(uint32_t address, void *vcontext) |
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296 { |
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297 uint16_t word = cell_image_read16(address & 0xFFFFFE, vcontext); |
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298 if (address & 1) { |
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299 return word; |
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300 } |
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301 return word >> 8; |
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302 } |
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303 |
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304 static void *cell_image_write16(uint32_t address, void *vcontext, uint16_t value) |
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305 { |
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306 address = cell_image_translate_address(address); |
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307 m68k_context *m68k = vcontext; |
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308 genesis_context *gen = m68k->system; |
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309 segacd_context *cd = gen->expansion; |
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310 if (m68k->mem_pointers[cd->memptr_start_index + 1]) { |
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311 m68k->mem_pointers[cd->memptr_start_index + 1][address>>1] = value; |
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312 } |
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313 return vcontext; |
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314 } |
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315 |
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316 static void *cell_image_write8(uint32_t address, void *vcontext, uint8_t value) |
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317 { |
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318 uint32_t byte = address & 1; |
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319 address = cell_image_translate_address(address); |
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320 m68k_context *m68k = vcontext; |
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321 genesis_context *gen = m68k->system; |
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322 segacd_context *cd = gen->expansion; |
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323 if (m68k->mem_pointers[cd->memptr_start_index + 1]) { |
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324 if (byte) { |
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325 m68k->mem_pointers[cd->memptr_start_index + 1][address>>1] &= 0xFF00; |
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326 m68k->mem_pointers[cd->memptr_start_index + 1][address>>1] |= value; |
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327 } else { |
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328 m68k->mem_pointers[cd->memptr_start_index + 1][address>>1] &= 0x00FF; |
76ea19e8b1a9
Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
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parents:
2120
diff
changeset
|
329 m68k->mem_pointers[cd->memptr_start_index + 1][address>>1] |= value << 8; |
76ea19e8b1a9
Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
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parents:
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diff
changeset
|
330 } |
76ea19e8b1a9
Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
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parents:
2120
diff
changeset
|
331 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
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parents:
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diff
changeset
|
332 return vcontext; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
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diff
changeset
|
333 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
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diff
changeset
|
334 |
2127
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
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2126
diff
changeset
|
335 static void cdd_run(segacd_context *cd, uint32_t cycle) |
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
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changeset
|
336 { |
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
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changeset
|
337 cdd_mcu_run(&cd->cdd, cycle, cd->gate_array + GA_CDD_CTRL, &cd->cdc, &cd->fader); |
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
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changeset
|
338 lc8951_run(&cd->cdc, cycle); |
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
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changeset
|
339 } |
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
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diff
changeset
|
340 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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diff
changeset
|
341 static uint8_t pcm_read8(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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changeset
|
342 { |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
343 m68k_context *m68k = vcontext; |
cfd53c94fffb
Initial stab at RF5C164 emulation
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2080
diff
changeset
|
344 segacd_context *cd = m68k->system; |
cfd53c94fffb
Initial stab at RF5C164 emulation
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diff
changeset
|
345 if (address & 1) { |
2127
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
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2126
diff
changeset
|
346 //need to run CD drive because there may be a PCM DMA underway |
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
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parents:
2126
diff
changeset
|
347 cdd_run(cd, m68k->current_cycle); |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
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diff
changeset
|
348 rf5c164_run(&cd->pcm, m68k->current_cycle); |
cfd53c94fffb
Initial stab at RF5C164 emulation
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diff
changeset
|
349 return rf5c164_read(&cd->pcm, address >> 1); |
cfd53c94fffb
Initial stab at RF5C164 emulation
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diff
changeset
|
350 } else { |
cfd53c94fffb
Initial stab at RF5C164 emulation
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parents:
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diff
changeset
|
351 return 0xFF; |
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
352 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
353 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
354 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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diff
changeset
|
355 static uint16_t pcm_read16(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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|
356 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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changeset
|
357 return 0xFF00 | pcm_read8(address+1, vcontext); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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changeset
|
358 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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diff
changeset
|
359 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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diff
changeset
|
360 static void *pcm_write8(uint32_t address, void *vcontext, uint8_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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diff
changeset
|
361 { |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
362 m68k_context *m68k = vcontext; |
cfd53c94fffb
Initial stab at RF5C164 emulation
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parents:
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diff
changeset
|
363 segacd_context *cd = m68k->system; |
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
364 if (address & 1) { |
2127
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents:
2126
diff
changeset
|
365 //need to run CD drive because there may be a PCM DMA underway |
1bf30397dd45
Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents:
2126
diff
changeset
|
366 cdd_run(cd, m68k->current_cycle); |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
367 rf5c164_run(&cd->pcm, m68k->current_cycle); |
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
368 rf5c164_write(&cd->pcm, address >> 1, value); |
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
369 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
370 return vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
371 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
372 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
373 static void *pcm_write16(uint32_t address, void *vcontext, uint16_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
374 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
375 return pcm_write8(address+1, vcontext, value); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
376 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
377 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
378 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
379 static void timers_run(segacd_context *cd, uint32_t cycle) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
380 { |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
381 if (cycle <= cd->stopwatch_cycle) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
382 return; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
383 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
384 uint32_t ticks = (cycle - cd->stopwatch_cycle) / TIMER_TICK_CLKS; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
385 cd->stopwatch_cycle += ticks * TIMER_TICK_CLKS; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
386 cd->gate_array[GA_STOP_WATCH] += ticks; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
387 cd->gate_array[GA_STOP_WATCH] &= 0xFFF; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
388 if (ticks && !cd->timer_value) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
389 --ticks; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
390 cd->timer_value = cd->gate_array[GA_TIMER]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
391 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
392 if (ticks && cd->timer_value) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
393 while (ticks >= (cd->timer_value + 1)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
394 ticks -= cd->timer_value + 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
395 cd->timer_value = cd->gate_array[GA_TIMER]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
396 cd->timer_pending = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
397 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
398 cd->timer_value -= ticks; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
399 if (!cd->timer_value) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
400 cd->timer_pending = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
401 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
402 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
403 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
404 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
405 static uint32_t next_timer_int(segacd_context *cd) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
406 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
407 if (cd->timer_pending) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
408 return cd->stopwatch_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
409 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
410 if (cd->timer_value) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
411 return cd->stopwatch_cycle + TIMER_TICK_CLKS * cd->timer_value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
412 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
413 if (cd->gate_array[GA_TIMER]) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
414 return cd->stopwatch_cycle + TIMER_TICK_CLKS * (cd->gate_array[GA_TIMER] + 1); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
415 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
416 return CYCLE_NEVER; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
417 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
418 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
419 static void calculate_target_cycle(m68k_context * context) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
420 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
421 segacd_context *cd = context->system; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
422 context->int_cycle = CYCLE_NEVER; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
423 uint8_t mask = context->status & 0x7; |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
424 uint32_t cdc_cycle = CYCLE_NEVER; |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
425 if (mask < 6) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
426 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN6) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
427 uint32_t subcode_cycle = cd->cdd.subcode_int_pending ? context->current_cycle : cd->cdd.next_subcode_int_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
428 if (subcode_cycle != CYCLE_NEVER) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
429 context->int_cycle = subcode_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
430 context->int_num = 6; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
431 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
432 } |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
433 if (mask < 5) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
434 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN5) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
435 cdc_cycle = lc8951_next_interrupt(&cd->cdc); |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
436 //CDC interrupts only generated on falling edge of !INT signal |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
437 if (cd->cdc_int_ack) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
438 if (cdc_cycle > cd->cdc.cycle) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
439 cd->cdc_int_ack = 0; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
440 } else { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
441 cdc_cycle = CYCLE_NEVER; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
442 } |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
443 } |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
444 if (cdc_cycle < context->int_cycle) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
445 context->int_cycle = cdc_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
446 context->int_num = 5; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
447 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
448 } |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
449 if (mask < 4) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
450 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN4) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
451 uint32_t cdd_cycle = cd->cdd.int_pending ? context->current_cycle : cd->cdd.next_int_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
452 if (cdd_cycle < context->int_cycle) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
453 context->int_cycle = cdd_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
454 context->int_num = 4; |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
455 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
456 } |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
457 if (mask < 3) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
458 uint32_t next_timer; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
459 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN3) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
460 uint32_t next_timer_cycle = next_timer_int(cd); |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
461 if (next_timer_cycle < context->int_cycle) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
462 context->int_cycle = next_timer_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
463 context->int_num = 3; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
464 } |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
465 } |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
466 if (mask < 2) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
467 if (cd->int2_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
468 context->int_cycle = cd->int2_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
469 context->int_num = 2; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
470 } |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
471 if (mask < 1) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
472 if (cd->graphics_int_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN1)) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
473 context->int_cycle = cd->graphics_int_cycle; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
474 context->int_num = 1; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
475 } |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
476 } |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
477 } |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
478 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
479 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
480 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
481 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
482 if (context->int_cycle > context->current_cycle && context->int_pending == INT_PENDING_SR_CHANGE) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
483 context->int_pending = INT_PENDING_NONE; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
484 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
485 if (context->current_cycle >= context->sync_cycle) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
486 context->should_return = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
487 context->target_cycle = context->current_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
488 return; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
489 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
490 if (context->status & M68K_STATUS_TRACE || context->trace_pending) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
491 context->target_cycle = context->current_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
492 return; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
493 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
494 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle; |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
495 if (context->target_cycle == cdc_cycle && context->int_num == 5) { |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
496 uint32_t before = context->target_cycle - 2 * cd->cdc.clock_step; |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
497 if (before > context->current_cycle) { |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
498 context->target_cycle = context->sync_cycle = before; |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
499 } |
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
500 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
501 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
502 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
503 static uint16_t sub_gate_read16(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
504 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
505 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
506 segacd_context *cd = m68k->system; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
507 uint32_t reg = address >> 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
508 switch (reg) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
509 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
510 case GA_SUB_CPU_CTRL: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
511 uint16_t value = cd->gate_array[reg] & 0xFFFE; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
512 if (cd->periph_reset_cycle == CYCLE_NEVER || (m68k->current_cycle - cd->periph_reset_cycle) > SCD_PERIPH_RESET_CLKS) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
513 value |= BIT_PRES; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
514 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
515 return value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
516 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
517 case GA_MEM_MODE: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
518 return cd->gate_array[reg] & 0xFF1F; |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
519 case GA_CDC_CTRL: |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
520 cdd_run(cd, m68k->current_cycle); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
521 return cd->gate_array[reg] | cd->cdc.ar; |
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
522 case GA_CDC_REG_DATA: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
523 cdd_run(cd, m68k->current_cycle); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
524 return lc8951_reg_read(&cd->cdc); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
525 case GA_CDC_HOST_DATA: { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
526 cdd_run(cd, m68k->current_cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
527 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
528 if (dst == DST_SUB_CPU) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
529 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
530 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
531 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
532 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
533 calculate_target_cycle(cd->m68k); |
2068
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
534 |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
535 } |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
536 return cd->gate_array[reg]; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
537 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
538 case GA_STOP_WATCH: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
539 case GA_TIMER: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
540 timers_run(cd, m68k->current_cycle); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
541 return cd->gate_array[reg]; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
542 case GA_CDD_STATUS0: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
543 case GA_CDD_STATUS1: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
544 case GA_CDD_STATUS2: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
545 case GA_CDD_STATUS3: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
546 case GA_CDD_STATUS4: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
547 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
548 return cd->gate_array[reg]; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
549 break; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
550 case GA_FONT_DATA0: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
551 case GA_FONT_DATA1: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
552 case GA_FONT_DATA2: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
553 case GA_FONT_DATA3: { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
554 uint16_t shift = 4 * (3 - (reg - GA_FONT_DATA0)); |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
555 uint16_t value = 0; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
556 uint16_t fg = cd->gate_array[GA_FONT_COLOR] >> 4; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
557 uint16_t bg = cd->gate_array[GA_FONT_COLOR] & 0xF; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
558 for (int i = 0; i < 4; i++) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
559 uint16_t pixel = 0; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
560 if (cd->gate_array[GA_FONT_BITS] & 1 << (shift + i)) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
561 pixel = fg; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
562 } else { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
563 pixel = bg; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
564 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
565 value |= pixel << (i * 4); |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
566 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
567 return value; |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
568 } |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
569 case GA_STAMP_SIZE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
570 case GA_IMAGE_BUFFER_LINES: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
571 //these two have bits that change based on graphics operations |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
572 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
573 return cd->gate_array[reg]; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
574 case GA_TRACE_VECTOR_BASE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
575 //write only |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
576 return 0xFFFF; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
577 default: |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
578 if (reg >= GA_SUBCODE_MIRROR) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
579 return cd->gate_array[GA_SUBCODE_START + (reg & 0x3F)]; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
580 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
581 return cd->gate_array[reg]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
582 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
583 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
584 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
585 static uint8_t sub_gate_read8(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
586 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
587 uint16_t val = sub_gate_read16(address, vcontext); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
588 return address & 1 ? val : val >> 8; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
589 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
590 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
591 static void *sub_gate_write16(uint32_t address, void *vcontext, uint16_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
592 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
593 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
594 segacd_context *cd = m68k->system; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
595 uint32_t reg = address >> 1; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
596 switch (reg) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
597 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
598 case GA_SUB_CPU_CTRL: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
599 cd->gate_array[reg] &= 0xF0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
600 cd->gate_array[reg] |= value & (BIT_LEDG|BIT_LEDR); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
601 if (value & BIT_PRES) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
602 cd->periph_reset_cycle = m68k->current_cycle; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
603 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
604 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
605 case GA_MEM_MODE: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
606 uint16_t changed = value ^ cd->gate_array[reg]; |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
607 uint8_t old_main_has_word2m = cd->main_has_word2m; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
608 if (value & BIT_RET) { |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
609 cd->main_has_word2m = 1; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
610 } |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
611 uint8_t old_bank_toggle = cd->bank_toggle; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
612 cd->bank_toggle = value & BIT_RET; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
613 genesis_context *gen = cd->genesis; |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
614 cd->gate_array[reg] &= 0xFFC0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
615 if (changed & BIT_MEM_MODE) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
616 //FIXME: ram banks are supposed to be interleaved when in 2M mode |
2120
91ed3c4cdfd9
Fix the regression in Stellar Fire while still passing RET/DMNA tests
Michael Pavone <pavone@retrodev.com>
parents:
2119
diff
changeset
|
617 cd->main_swap_request = cd->bank_toggle && !old_bank_toggle; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
618 if (value & BIT_MEM_MODE) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
619 //switch to 1M mode |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
620 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = (value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
621 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
622 m68k->mem_pointers[0] = NULL; |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
623 m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 0x10000; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
624 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_RET|BIT_MEM_MODE); |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
625 if (cd->main_swap_request) { |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
626 cd->gate_array[reg] |= BIT_DMNA; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
627 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
628 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
629 //switch to 2M mode |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
630 if (cd->main_has_word2m) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
631 //Main CPU will have word ram |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
632 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
633 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
634 m68k->mem_pointers[0] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
635 m68k->mem_pointers[1] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
636 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
637 //sub cpu will have word ram |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
638 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
639 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
640 m68k->mem_pointers[0] = cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
641 m68k->mem_pointers[1] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
642 } |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
643 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_MEM_MODE); |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
644 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
645 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
646 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
647 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
648 } else if (value & BIT_MEM_MODE) { |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
649 //1M mode |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
650 if (old_bank_toggle != cd->bank_toggle) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
651 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = (value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
652 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 0x10000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
653 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
654 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
655 cd->main_swap_request = 0; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
656 } |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
657 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_RET|BIT_MEM_MODE); |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
658 if (cd->main_swap_request) { |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
659 cd->gate_array[reg] |= BIT_DMNA; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
660 } |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
661 } else { |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
662 //2M mode |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
663 if (old_main_has_word2m != cd->main_has_word2m) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
664 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
665 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
666 m68k->mem_pointers[0] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
667 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
668 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
669 } |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
670 cd->gate_array[reg] |= value & MASK_PRIORITY; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
671 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
672 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
673 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
674 } |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
675 case GA_CDC_CTRL: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
676 cdd_run(cd, m68k->current_cycle); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
677 lc8951_ar_write(&cd->cdc, value); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
678 //cd->gate_array[reg] &= 0xC000; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
679 //apparently this clears EDT, should it also clear DSR? |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
680 cd->gate_array[reg] = value & 0x0700; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
681 cd->cdc_dst_low = 0; |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
682 break; |
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
683 case GA_CDC_REG_DATA: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
684 cdd_run(cd, m68k->current_cycle); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
685 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
686 lc8951_reg_write(&cd->cdc, value); |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
687 calculate_target_cycle(m68k); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
688 break; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
689 case GA_CDC_DMA_ADDR: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
690 cdd_run(cd, m68k->current_cycle); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
691 cd->gate_array[reg] = value; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
692 cd->cdc_dst_low = 0; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
693 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
694 case GA_STOP_WATCH: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
695 //docs say you should only write zero to reset |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
696 //mcd-verificator comments suggest any value will reset |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
697 timers_run(cd, m68k->current_cycle); |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
698 cd->gate_array[reg] = 0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
699 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
700 case GA_COMM_FLAG: |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
701 cd->gate_array[reg] &= 0xFF00; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
702 cd->gate_array[reg] |= value & 0xFF; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
703 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
704 case GA_COMM_STATUS0: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
705 case GA_COMM_STATUS1: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
706 case GA_COMM_STATUS2: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
707 case GA_COMM_STATUS3: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
708 case GA_COMM_STATUS4: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
709 case GA_COMM_STATUS5: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
710 case GA_COMM_STATUS6: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
711 case GA_COMM_STATUS7: |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
712 //no effects for these other than saving the value |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
713 cd->gate_array[reg] = value; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
714 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
715 case GA_TIMER: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
716 timers_run(cd, m68k->current_cycle); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
717 cd->gate_array[reg] = value & 0xFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
718 calculate_target_cycle(m68k); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
719 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
720 case GA_INT_MASK: |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
721 if (!(cd->gate_array[reg] & BIT_MASK_IEN6)) { |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
722 //subcode interrupts can't be made pending when they are disabled in this reg |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
723 cd->cdd.subcode_int_pending = 0; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
724 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
725 cd->gate_array[reg] = value & (BIT_MASK_IEN6|BIT_MASK_IEN5|BIT_MASK_IEN4|BIT_MASK_IEN3|BIT_MASK_IEN2|BIT_MASK_IEN1); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
726 calculate_target_cycle(m68k); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
727 break; |
2080 | 728 case GA_CDD_FADER: |
729 cdd_run(cd, m68k->current_cycle); | |
730 value &= 0x7FFF; | |
731 cdd_fader_attenuation_write(&cd->fader, value); | |
732 cd->gate_array[reg] &= 0x8000; | |
733 cd->gate_array[reg] |= value; | |
734 break; | |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
735 case GA_CDD_CTRL: { |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
736 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
737 uint16_t changed = cd->gate_array[reg] ^ value; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
738 if (changed & BIT_HOCK) { |
2073
c69e42444f96
Fix some cycle adjustment stuff and an off-by one on hte TOCT response
Michael Pavone <pavone@retrodev.com>
parents:
2069
diff
changeset
|
739 cd->gate_array[reg] &= ~BIT_HOCK; |
c69e42444f96
Fix some cycle adjustment stuff and an off-by one on hte TOCT response
Michael Pavone <pavone@retrodev.com>
parents:
2069
diff
changeset
|
740 cd->gate_array[reg] |= value & BIT_HOCK; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
741 if (value & BIT_HOCK) { |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
742 cdd_hock_enabled(&cd->cdd); |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
743 } else { |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
744 cdd_hock_disabled(&cd->cdd); |
2080 | 745 cd->gate_array[reg] |= BIT_MUTE; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
746 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
747 calculate_target_cycle(m68k); |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
748 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
749 break; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
750 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
751 case GA_CDD_CMD0: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
752 case GA_CDD_CMD1: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
753 case GA_CDD_CMD2: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
754 case GA_CDD_CMD3: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
755 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
756 cd->gate_array[reg] = value & 0x0F0F; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
757 break; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
758 case GA_CDD_CMD4: |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
759 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
760 cd->gate_array[reg] = value & 0x0F0F; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
761 cdd_mcu_start_cmd_recv(&cd->cdd, cd->gate_array + GA_CDD_CTRL); |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
762 break; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
763 case GA_FONT_COLOR: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
764 cd->gate_array[reg] = value & 0xFF; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
765 break; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
766 case GA_FONT_BITS: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
767 cd->gate_array[reg] = value; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
768 break; |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
769 case GA_STAMP_SIZE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
770 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
771 cd->gate_array[reg] &= BIT_GRON; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
772 cd->gate_array[reg] |= value & (BIT_SMS|BIT_STS|BIT_RPT); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
773 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
774 case GA_STAMP_MAP_BASE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
775 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
776 cd->gate_array[reg] = value & 0xFFE0; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
777 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
778 case GA_IMAGE_BUFFER_VCELLS: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
779 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
780 cd->gate_array[reg] = value & 0x1F; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
781 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
782 case GA_IMAGE_BUFFER_START: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
783 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
784 cd->gate_array[reg] = value & 0xFFF8; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
785 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
786 case GA_IMAGE_BUFFER_OFFSET: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
787 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
788 cd->gate_array[reg] = value & 0x3F; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
789 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
790 case GA_IMAGE_BUFFER_HDOTS: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
791 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
792 cd->gate_array[reg] = value & 0x1FF; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
793 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
794 case GA_IMAGE_BUFFER_LINES: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
795 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
796 cd->gate_array[reg] = value & 0xFF; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
797 break; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
798 case GA_TRACE_VECTOR_BASE: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
799 cd_graphics_run(cd, m68k->current_cycle); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
800 cd->gate_array[reg] = value & 0xFFFE; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
801 cd_graphics_start(cd); |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
802 break; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
803 default: |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
804 printf("Unhandled gate array write %X:%X\n", address, value); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
805 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
806 return vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
807 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
808 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
809 static void *sub_gate_write8(uint32_t address, void *vcontext, uint8_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
810 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
811 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
812 segacd_context *cd = m68k->system; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
813 uint32_t reg = (address & 0x1FF) >> 1; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
814 uint16_t value16; |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
815 switch (address >> 1) |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
816 { |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
817 case GA_MEM_MODE: |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
818 case GA_CDC_HOST_DATA: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
819 case GA_CDC_DMA_ADDR: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
820 case GA_STOP_WATCH: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
821 case GA_COMM_FLAG: |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
822 case GA_TIMER: |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
823 case GA_CDD_FADER: |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
824 case GA_FONT_COLOR: |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
825 //these registers treat all writes as word-wide |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
826 value16 = value | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
827 break; |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
828 case GA_CDC_CTRL: |
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
829 if (address & 1) { |
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
830 lc8951_ar_write(&cd->cdc, value); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
831 return vcontext; |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
832 } else { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
833 value16 = cd->cdc.ar | (value << 8); |
2058
70260f6051dd
Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents:
2057
diff
changeset
|
834 } |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
835 break; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
836 case GA_CDD_CMD4: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
837 if (!address) { |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
838 //byte write to $FF804A should not trigger transfer |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
839 cdd_run(cd, m68k->current_cycle); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
840 cd->gate_array[reg] &= 0x0F; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
841 cd->gate_array[reg] |= (value << 8 & 0x0F00); |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
842 return vcontext; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
843 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
844 //intentional fallthrough for $FF804B |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
845 default: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
846 if (address & 1) { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
847 value16 = cd->gate_array[reg] & 0xFF00 | value; |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
848 } else { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
849 value16 = cd->gate_array[reg] & 0xFF | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
850 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
851 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
852 return sub_gate_write16(address, vcontext, value16); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
853 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
854 |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
855 static uint8_t handle_cdc_byte(void *vsys, uint8_t value) |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
856 { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
857 segacd_context *cd = vsys; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
858 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
859 //host reg is already full, pause transfer |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
860 return 0; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
861 } |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
862 if (cd->cdc.cycle == cd->cdc.transfer_end) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
863 cd->gate_array[GA_CDC_CTRL] |= BIT_EDT; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
864 printf("EDT set at %u\n", cd->cdc.cycle); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
865 } |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
866 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
867 if (!(cd->cdc_dst_low & 1)) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
868 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
869 cd->gate_array[GA_CDC_HOST_DATA] |= value << 8; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
870 cd->cdc_dst_low++; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
871 if (dest != DST_PCM_RAM) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
872 //PCM RAM writes a byte at a time |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
873 return 1; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
874 } |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
875 } else { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
876 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF00; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
877 cd->gate_array[GA_CDC_HOST_DATA] |= value; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
878 } |
2068
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
879 |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
880 uint32_t dma_addr = cd->gate_array[GA_CDC_DMA_ADDR] << 3; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
881 dma_addr |= cd->cdc_dst_low; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
882 switch (dest) |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
883 { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
884 case DST_MAIN_CPU: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
885 case DST_SUB_CPU: |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
886 cd->cdc_dst_low = 0; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
887 cd->gate_array[GA_CDC_CTRL] |= BIT_DSR; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
888 break; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
889 case DST_PCM_RAM: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
890 dma_addr &= (1 << 13) - 1; |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
891 rf5c164_run(&cd->pcm, cd->cdc.cycle); |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
892 rf5c164_write(&cd->pcm, 0x1000 | (dma_addr >> 1), value); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
893 dma_addr += 2; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
894 cd->cdc_dst_low = dma_addr & 7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
895 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
896 break; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
897 case DST_PROG_RAM: |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
898 cd->prog_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA]; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
899 m68k_invalidate_code_range(cd->m68k, dma_addr - 1, dma_addr + 1); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
900 dma_addr++; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
901 cd->cdc_dst_low = dma_addr & 7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
902 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
903 break; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
904 case DST_WORD_RAM: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
905 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
906 //1M mode, write to bank assigned to Sub CPU |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
907 dma_addr &= (1 << 17) - 1; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
908 cd->m68k->mem_pointers[1][dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA]; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
909 m68k_invalidate_code_range(cd->m68k, 0x0C0000 + dma_addr - 1, 0x0C0000 + dma_addr + 1); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
910 } else { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
911 //2M mode, check if Sub CPU has access |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
912 if (!(cd->gate_array[GA_MEM_MODE] & BIT_RET)) { |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
913 cd_graphics_run(cd, cd->cdc.cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
914 dma_addr &= (1 << 18) - 1; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
915 cd->word_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA]; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
916 m68k_invalidate_code_range(cd->m68k, 0x080000 + dma_addr, 0x080000 + dma_addr + 1); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
917 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
918 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
919 dma_addr++; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
920 cd->cdc_dst_low = dma_addr & 7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
921 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
922 break; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
923 default: |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
924 printf("Invalid CDC transfer destination %d\n", dest); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
925 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
926 return 1; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
927 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
928 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
929 static uint8_t can_main_access_prog(segacd_context *cd) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
930 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
931 //TODO: use actual busack |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
932 return cd->busreq || !cd->reset; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
933 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
934 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
935 static void scd_peripherals_run(segacd_context *cd, uint32_t cycle) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
936 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
937 timers_run(cd, cycle); |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2061
diff
changeset
|
938 cdd_run(cd, cycle); |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
939 cd_graphics_run(cd, cycle); |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
940 rf5c164_run(&cd->pcm, cycle); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
941 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
942 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
943 static m68k_context *sync_components(m68k_context * context, uint32_t address) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
944 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
945 segacd_context *cd = context->system; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
946 scd_peripherals_run(cd, context->current_cycle); |
2104
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
947 if (address && cd->enter_debugger) { |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
948 genesis_context *gen = cd->genesis; |
2106
d2989e32c026
Fix bug in Sub CPU debugger suport
Michael Pavone <pavone@retrodev.com>
parents:
2104
diff
changeset
|
949 cd->enter_debugger = 0; |
2104
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
950 if (gen->header.debugger_type == DEBUGGER_NATIVE) { |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
951 debugger(context, address); |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
952 } else { |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
953 gdb_debug_enter(context, address); |
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
954 } |
2080 | 955 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
956 switch (context->int_ack) |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
957 { |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
958 case 1: |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
959 cd->graphics_int_cycle = CYCLE_NEVER; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
960 break; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
961 case 2: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
962 cd->int2_cycle = CYCLE_NEVER; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
963 break; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
964 case 3: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
965 cd->timer_pending = 0; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
966 break; |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
967 case 4: |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
968 cd->cdd.int_pending = 0; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
969 break; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
970 case 5: |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
971 cd->cdc_int_ack = 1; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
972 break; |
2116
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
973 case 6: |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
974 cd->cdd.subcode_int_pending = 0; |
cd057d6fe030
Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents:
2111
diff
changeset
|
975 break; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
976 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
977 context->int_ack = 0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
978 calculate_target_cycle(context); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
979 return context; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
980 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
981 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
982 void scd_run(segacd_context *cd, uint32_t cycle) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
983 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
984 uint8_t m68k_run = !can_main_access_prog(cd); |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
985 while (cycle > cd->m68k->current_cycle) { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
986 if (m68k_run) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
987 uint32_t start = cd->m68k->current_cycle; |
2104
ff32a90260c9
Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents:
2099
diff
changeset
|
988 cd->m68k->sync_cycle = cd->enter_debugger ? cd->m68k->current_cycle + 1 : cycle; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
989 if (cd->need_reset) { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
990 cd->need_reset = 0; |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
991 m68k_reset(cd->m68k); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
992 } else { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
993 calculate_target_cycle(cd->m68k); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
994 resume_68k(cd->m68k); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
995 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
996 } else { |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
997 cd->m68k->current_cycle = cycle; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
998 } |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
999 scd_peripherals_run(cd, cd->m68k->current_cycle); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1000 } |
2094
ca6fc8c8dc60
Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2087
diff
changeset
|
1001 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1002 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1003 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1004 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1005 { |
2055
c4d066d798c4
Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents:
2054
diff
changeset
|
1006 return ((uint64_t)cycle) * ((uint64_t)SCD_MCLKS) / ((uint64_t)gen->normal_clock); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1007 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1008 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1009 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1010 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1011 deduction = gen_cycle_to_scd(deduction, cd->genesis); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1012 cd->m68k->current_cycle -= deduction; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1013 cd->stopwatch_cycle -= deduction; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1014 if (deduction >= cd->int2_cycle) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1015 cd->int2_cycle = 0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1016 } else if (cd->int2_cycle != CYCLE_NEVER) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1017 cd->int2_cycle -= deduction; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1018 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1019 if (deduction >= cd->periph_reset_cycle) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1020 cd->periph_reset_cycle = CYCLE_NEVER; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1021 } else if (cd->periph_reset_cycle != CYCLE_NEVER) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1022 cd->periph_reset_cycle -= deduction; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1023 } |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
1024 cdd_mcu_adjust_cycle(&cd->cdd, deduction); |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1025 lc8951_adjust_cycles(&cd->cdc, deduction); |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1026 cd->graphics_cycle -= deduction; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1027 if (cd->graphics_int_cycle != CYCLE_NEVER) { |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1028 if (cd->graphics_int_cycle > deduction) { |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1029 cd->graphics_int_cycle -= deduction; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1030 } else { |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1031 cd->graphics_int_cycle = 0; |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1032 } |
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1033 } |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
1034 cd->pcm.cycle -= deduction; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1035 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1036 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1037 static uint16_t main_gate_read16(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1038 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1039 m68k_context *m68k = vcontext; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1040 genesis_context *gen = m68k->system; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1041 segacd_context *cd = gen->expansion; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1042 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1043 scd_run(cd, scd_cycle); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1044 uint32_t offset = (address & 0x1FF) >> 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1045 switch (offset) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1046 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1047 case GA_SUB_CPU_CTRL: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1048 uint16_t value = 0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1049 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1050 value |= BIT_IEN2; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1051 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1052 if (cd->int2_cycle != CYCLE_NEVER) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1053 value |= BIT_IFL2; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1054 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1055 if (can_main_access_prog(cd)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1056 value |= BIT_SBRQ; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1057 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1058 if (cd->reset) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1059 value |= BIT_SRES; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1060 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1061 return value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1062 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1063 case GA_MEM_MODE: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1064 //Main CPU can't read priority mode bits |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1065 return cd->gate_array[offset] & 0xFFE7; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1066 case GA_HINT_VECTOR: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1067 return cd->rom_mut[0x72/2]; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1068 case GA_CDC_HOST_DATA: { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1069 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7; |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1070 if (dst == DST_MAIN_CPU) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1071 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) { |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1072 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR; |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1073 lc8951_resume_transfer(&cd->cdc, scd_cycle); |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1074 } else { |
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1075 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle); |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1076 } |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1077 calculate_target_cycle(cd->m68k); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1078 } |
2066
a61a8a87410c
Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents:
2065
diff
changeset
|
1079 return cd->gate_array[offset]; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1080 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1081 case GA_CDC_DMA_ADDR: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1082 //TODO: open bus maybe? |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1083 return 0xFFFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1084 default: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1085 if (offset < GA_TIMER) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1086 return cd->gate_array[offset]; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1087 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1088 //TODO: open bus maybe? |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1089 return 0xFFFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1090 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1091 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1092 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1093 static uint8_t main_gate_read8(uint32_t address, void *vcontext) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1094 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1095 uint16_t val = main_gate_read16(address & 0xFE, vcontext); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1096 return address & 1 ? val : val >> 8; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1097 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1098 |
2068
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1099 static void dump_prog_ram(segacd_context *cd) |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1100 { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1101 static int dump_count; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1102 char fname[256]; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1103 sprintf(fname, "prog_ram_%d.bin", dump_count++); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1104 FILE *f = fopen(fname, "wb"); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1105 if (f) { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1106 uint32_t last = 256*1024-1; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1107 for(; last > 0; --last) |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1108 { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1109 if (cd->prog_ram[last]) { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1110 break; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1111 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1112 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1113 for (uint32_t i = 0; i <= last; i++) |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1114 { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1115 uint8_t pair[2]; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1116 pair[0] = cd->prog_ram[i] >> 8; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1117 pair[1] = cd->prog_ram[i]; |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1118 fwrite(pair, 1, sizeof(pair), f); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1119 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1120 |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1121 fclose(f); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1122 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1123 } |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1124 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1125 static void *main_gate_write16(uint32_t address, void *vcontext, uint16_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1126 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1127 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1128 genesis_context *gen = m68k->system; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1129 segacd_context *cd = gen->expansion; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1130 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1131 scd_run(cd, scd_cycle); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1132 uint32_t reg = (address & 0x1FF) >> 1; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1133 switch (reg) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1134 { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1135 case GA_SUB_CPU_CTRL: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1136 uint8_t old_access = can_main_access_prog(cd); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1137 cd->busreq = value & BIT_SBRQ; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1138 uint8_t old_reset = cd->reset; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1139 cd->reset = value & BIT_SRES; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1140 if (cd->reset && !old_reset) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1141 cd->need_reset = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1142 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1143 if (value & BIT_IFL2) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1144 cd->int2_cycle = scd_cycle; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1145 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1146 /*cd->gate_array[reg] &= 0x7FFF; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1147 cd->gate_array[reg] |= value & 0x8000;*/ |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1148 uint8_t new_access = can_main_access_prog(cd); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1149 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1150 if (new_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1151 if (!old_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1152 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1153 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1154 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1155 } else if (old_access) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1156 m68k->mem_pointers[cd->memptr_start_index] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1157 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1158 m68k_invalidate_code_range(cd->m68k, bank * 0x20000, (bank + 1) * 0x20000); |
2068
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1159 if (!new_access) { |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1160 dump_prog_ram(cd); |
f573f2c31bc9
Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents:
2066
diff
changeset
|
1161 } |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1162 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1163 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1164 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1165 case GA_MEM_MODE: { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1166 uint16_t changed = cd->gate_array[reg] ^ value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1167 //Main CPU can't write priority mode bits, MODE or RET |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1168 cd->gate_array[reg] &= 0x001F; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1169 cd->gate_array[reg] |= value & 0xFFC0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1170 if ((cd->gate_array[reg] & BIT_MEM_MODE)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1171 //1M mode |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1172 if (!(value & BIT_DMNA)) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1173 cd->gate_array[reg] |= BIT_DMNA; |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1174 cd->main_swap_request = 1; |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1175 } else { |
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1176 cd->main_has_word2m = 0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1177 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1178 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1179 //2M mode |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1180 if (changed & value & BIT_DMNA) { |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1181 cd->gate_array[reg] |= BIT_DMNA; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1182 m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1183 m68k->mem_pointers[cd->memptr_start_index + 2] = NULL; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1184 cd->m68k->mem_pointers[0] = cd->word_ram; |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1185 cd->gate_array[reg] &= ~BIT_RET; |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1186 cd->main_has_word2m = 0; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1187 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1188 m68k_invalidate_code_range(m68k, cd->base + 0x200000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1189 m68k_invalidate_code_range(cd->m68k, 0x080000, 0x0C0000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1190 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1191 } |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1192 if (changed & MASK_PROG_BANK && can_main_access_prog(cd)) { |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1193 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3; |
2055
c4d066d798c4
Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents:
2054
diff
changeset
|
1194 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1195 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1196 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1197 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1198 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1199 case GA_HINT_VECTOR: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1200 cd->rom_mut[0x72/2] = value; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1201 break; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1202 case GA_COMM_FLAG: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1203 //Main CPU can only write the upper byte; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1204 cd->gate_array[reg] &= 0xFF; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1205 cd->gate_array[reg] |= value & 0xFF00; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1206 break; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1207 case GA_COMM_CMD0: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1208 case GA_COMM_CMD1: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1209 case GA_COMM_CMD2: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1210 case GA_COMM_CMD3: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1211 case GA_COMM_CMD4: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1212 case GA_COMM_CMD5: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1213 case GA_COMM_CMD6: |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1214 case GA_COMM_CMD7: |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1215 //no effects for these other than saving the value |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1216 cd->gate_array[reg] = value; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1217 break; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1218 default: |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1219 printf("Unhandled gate array write %X:%X\n", address, value); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1220 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1221 return vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1222 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1223 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1224 static void *main_gate_write8(uint32_t address, void *vcontext, uint8_t value) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1225 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1226 m68k_context *m68k = vcontext; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1227 genesis_context *gen = m68k->system; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1228 segacd_context *cd = gen->expansion; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1229 uint32_t reg = (address & 0x1FF) >> 1; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1230 uint16_t value16; |
2108
68d61ba1b762
Fix handling of byte writes to gate array regs from main CPU
Michael Pavone <pavone@retrodev.com>
parents:
2106
diff
changeset
|
1231 switch (reg) |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1232 { |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1233 case GA_SUB_CPU_CTRL: |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1234 if (address & 1) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1235 value16 = value; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1236 } else { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1237 value16 = value << 8; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1238 if (cd->reset) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1239 value16 |= BIT_SRES; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1240 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1241 if (cd->busreq) { |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1242 value16 |= BIT_SBRQ; |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1243 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1244 } |
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1245 break; |
2056
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1246 case GA_HINT_VECTOR: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1247 case GA_COMM_FLAG: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1248 //writes to these regs are always treated as word wide |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1249 value16 = value | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1250 break; |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1251 default: |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1252 if (address & 1) { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1253 value16 = cd->gate_array[reg] & 0xFF00 | value; |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1254 } else { |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1255 value16 = cd->gate_array[reg] & 0xFF | (value << 8); |
27bbfcb7850a
Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents:
2055
diff
changeset
|
1256 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1257 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1258 return main_gate_write16(address, vcontext, value16); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1259 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1260 |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1261 segacd_context *alloc_configure_segacd(system_media *media, uint32_t opts, uint8_t force_region, rom_info *info) |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1262 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1263 static memmap_chunk sub_cpu_map[] = { |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1264 {0x000000, 0x01FF00, 0xFFFFFF, .flags=MMAP_READ | MMAP_CODE, .write_16 = prog_ram_wp_write16, .write_8 = prog_ram_wp_write8}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1265 {0x01FF00, 0x080000, 0xFFFFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1266 {0x080000, 0x0C0000, 0x03FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 0, |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1267 .read_16 = word_ram_2M_read16, .write_16 = word_ram_2M_write16, .read_8 = word_ram_2M_read8, .write_8 = word_ram_2M_write8}, |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1268 {0x0C0000, 0x0E0000, 0x01FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 1, |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1269 .read_16 = word_ram_1M_read16, .write_16 = word_ram_1M_write16, .read_8 = word_ram_1M_read8, .write_8 = word_ram_1M_write8}, |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1270 {0xFE0000, 0xFF0000, 0x003FFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_ONLY_ODD}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1271 {0xFF0000, 0xFF8000, 0x003FFF, .read_16 = pcm_read16, .write_16 = pcm_write16, .read_8 = pcm_read8, .write_8 = pcm_write8}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1272 {0xFF8000, 0xFF8200, 0x0001FF, .read_16 = sub_gate_read16, .write_16 = sub_gate_write16, .read_8 = sub_gate_read8, .write_8 = sub_gate_write8} |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1273 }; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1274 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1275 segacd_context *cd = calloc(sizeof(segacd_context), 1); |
2083
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1276 uint32_t firmware_size; |
2123
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1277 uint8_t region = force_region; |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1278 if (!region) { |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1279 char * def_region = tern_find_path_default(config, "system\0default_region\0", (tern_val){.ptrval = "U"}, TVAL_PTR).ptrval; |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1280 if (!info->regions || (info->regions & translate_region_char(toupper(*def_region)))) { |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1281 region = translate_region_char(toupper(*def_region)); |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1282 } else { |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1283 region = info->regions; |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1284 } |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1285 } |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1286 const char *key; |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
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parents:
2122
diff
changeset
|
1287 if (region & REGION_E) { |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1288 key = "system\0scd_bios_eu\0"; |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1289 } else if (region & REGION_J) { |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1290 key = "system\0scd_bios_jp\0"; |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1291 } else { |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1292 key = "system\0scd_bios_us\0"; |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1293 } |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
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parents:
2122
diff
changeset
|
1294 char *bios_path = tern_find_path_default(config, key, (tern_val){.ptrval = "cdbios.bin"}, TVAL_PTR).ptrval; |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1295 cd->rom = (uint16_t *)read_bundled_file(bios_path, &firmware_size); |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1296 if (!cd->rom) { |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1297 fatal_error("Failed to load Sega CD BIOS from %s\n", bios_path); |
50385ae2617b
Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents:
2122
diff
changeset
|
1298 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
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1467
diff
changeset
|
1299 uint32_t adjusted_size = nearest_pow2(firmware_size); |
2083
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1300 if (adjusted_size != firmware_size) { |
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1301 cd->rom = realloc(cd->rom, adjusted_size); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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diff
changeset
|
1302 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
1303 cd->rom_mut = malloc(adjusted_size); |
1503
a763523dadf4
Added code for initializing a combined Genesis + Sega CD system when a Sega CD ISO is loaded
Michael Pavone <pavone@retrodev.com>
parents:
1502
diff
changeset
|
1304 byteswap_rom(adjusted_size, cd->rom); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
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diff
changeset
|
1305 memcpy(cd->rom_mut, cd->rom, adjusted_size); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1306 cd->rom_mut[0x72/2] = 0xFFFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents:
1504
diff
changeset
|
1307 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1308 //memset(info, 0, sizeof(*info)); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1309 //tern_node *db = get_rom_db(); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1310 //*info = configure_rom(db, media->buffer, media->size, media->chain ? media->chain->buffer : NULL, media->chain ? media->chain->size : 0, NULL, 0); |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1311 |
2083
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1312 cd->prog_ram = calloc(512*1024, 1); |
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1313 cd->word_ram = calloc(256*1024, 1); |
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1314 cd->pcm_ram = calloc(64*1024, 1); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1315 //TODO: Load state from file |
2083
372625dd9590
Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents:
2081
diff
changeset
|
1316 cd->bram = calloc(8*1024, 1); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1317 |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1318 |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
1319 sub_cpu_map[0].buffer = sub_cpu_map[1].buffer = cd->prog_ram; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1320 sub_cpu_map[4].buffer = cd->bram; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1321 m68k_options *mopts = malloc(sizeof(m68k_options)); |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1322 init_m68k_opts(mopts, sub_cpu_map, sizeof(sub_cpu_map) / sizeof(*sub_cpu_map), 4, sync_components); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1323 cd->m68k = init_68k_context(mopts, NULL); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1324 cd->m68k->system = cd; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1325 cd->int2_cycle = CYCLE_NEVER; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1326 cd->busreq = 1; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1327 cd->busack = 1; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1328 cd->need_reset = 1; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1329 cd->reset = 1; //active low, so reset is not active on start |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1330 cd->memptr_start_index = 0; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1331 cd->gate_array[1] = 1; |
2080 | 1332 cd->gate_array[GA_CDD_CTRL] = BIT_MUTE; //Data/mute flag is set on start |
2119
5ec2f97365a2
More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents:
2116
diff
changeset
|
1333 cd->main_has_word2m = 1; |
2065
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents:
2062
diff
changeset
|
1334 lc8951_init(&cd->cdc, handle_cdc_byte, cd); |
2061
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
1335 if (media->chain && media->type != MEDIA_CDROM) { |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
1336 media = media->chain; |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
1337 } |
7c1760b5b3e5
Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents:
2058
diff
changeset
|
1338 cdd_mcu_init(&cd->cdd, media); |
2069
8e51c0c3f2e3
Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents:
2068
diff
changeset
|
1339 cd_graphics_init(cd); |
2080 | 1340 cdd_fader_init(&cd->fader); |
2081
cfd53c94fffb
Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents:
2080
diff
changeset
|
1341 rf5c164_init(&cd->pcm, SCD_MCLKS, 4); |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1342 return cd; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
1343 } |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1344 |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1345 memmap_chunk *segacd_main_cpu_map(segacd_context *cd, uint8_t cart_boot, uint32_t *num_chunks) |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
1346 { |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1347 static memmap_chunk main_cpu_map[] = { |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1348 {0x000000, 0x020000, 0x01FFFF, .flags=MMAP_READ}, |
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1349 {0x020000, 0x040000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 0, |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1350 .read_16 = unmapped_prog_read16, .write_16 = unmapped_prog_write16, .read_8 = unmapped_prog_read8, .write_8 = unmapped_prog_write8}, |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1351 {0x040000, 0x060000, 0x01FFFF, .flags=MMAP_READ}, //first ROM alias |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1352 //TODO: additional ROM/prog RAM aliases |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1353 {0x200000, 0x220000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 1, |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1354 .read_16 = unmapped_word_read16, .write_16 = unmapped_word_write16, .read_8 = unmapped_word_read8, .write_8 = unmapped_word_write8}, |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1355 {0x220000, 0x240000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 2, |
2057
88deea42caf0
Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents:
2056
diff
changeset
|
1356 .read_16 = cell_image_read16, .write_16 = cell_image_write16, .read_8 = cell_image_read8, .write_8 = cell_image_write8}, |
2111
4be496489eda
Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents:
2108
diff
changeset
|
1357 {0xA12000, 0xA13000, 0xFFFFFF, .read_16 = main_gate_read16, .write_16 = main_gate_write16, .read_8 = main_gate_read8, .write_8 = main_gate_write8} |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
1358 }; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1359 for (int i = 0; i < sizeof(main_cpu_map) / sizeof(*main_cpu_map); i++) |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1360 { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1361 if (main_cpu_map[i].start < 0x800000) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1362 if (cart_boot) { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1363 main_cpu_map[i].start |= 0x400000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1364 main_cpu_map[i].end |= 0x400000; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1365 } else { |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1366 main_cpu_map[i].start &= 0x3FFFFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1367 main_cpu_map[i].end &= 0x3FFFFF; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1368 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1369 } |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1370 } |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1371 //TODO: support BRAM cart |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1372 main_cpu_map[0].buffer = cd->rom_mut; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
1373 main_cpu_map[2].buffer = cd->rom; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1374 main_cpu_map[1].buffer = cd->prog_ram; |
2054
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1375 main_cpu_map[3].buffer = cd->word_ram; |
8ee7ecbf3f21
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1504
diff
changeset
|
1376 main_cpu_map[4].buffer = cd->word_ram + 0x10000; |
1502
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1377 *num_chunks = sizeof(main_cpu_map) / sizeof(*main_cpu_map); |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents:
1467
diff
changeset
|
1378 return main_cpu_map; |
2564b6ba2e12
Initial skeleton of Sega CD memory handlers
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parents:
1467
diff
changeset
|
1379 } |