Mercurial > repos > blastem
annotate z80_to_x86.c @ 267:1788e3f29c28
Don't mix *H regs with the REX prefix
author | Mike Pavone <pavone@retrodev.com> |
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date | Thu, 02 May 2013 00:10:24 -0700 |
parents | 376df762ddf5 |
children | 6c2d7e003a55 |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 void z80_read_byte(); |
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19 void z80_read_word(); |
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20 void z80_write_byte(); |
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21 void z80_write_word_highfirst(); |
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22 void z80_write_word_lowfirst(); |
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23 void z80_save_context(); |
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24 void z80_native_addr(); |
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25 void z80_do_sync(); |
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26 void z80_handle_cycle_limit_int(); |
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27 void z80_retrans_stub(); |
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28 |
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29 uint8_t z80_size(z80inst * inst) |
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30 { |
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31 uint8_t reg = (inst->reg & 0x1F); |
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32 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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33 return reg < Z80_BC ? SZ_B : SZ_W; |
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34 } |
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35 //TODO: Handle any necessary special cases |
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36 return SZ_B; |
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37 } |
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38 |
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39 uint8_t z80_high_reg(uint8_t reg) |
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40 { |
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41 switch(reg) |
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42 { |
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43 case Z80_C: |
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44 case Z80_BC: |
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45 return Z80_B; |
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46 case Z80_E: |
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47 case Z80_DE: |
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48 return Z80_D; |
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49 case Z80_L: |
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50 case Z80_HL: |
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51 return Z80_H; |
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52 case Z80_IXL: |
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53 case Z80_IX: |
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54 return Z80_IXH; |
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55 case Z80_IYL: |
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56 case Z80_IY: |
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57 return Z80_IYH; |
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58 default: |
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59 return Z80_UNUSED; |
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60 } |
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61 } |
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62 |
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63 uint8_t z80_low_reg(uint8_t reg) |
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64 { |
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65 switch(reg) |
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66 { |
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67 case Z80_B: |
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68 case Z80_BC: |
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69 return Z80_C; |
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70 case Z80_D: |
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71 case Z80_DE: |
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72 return Z80_E; |
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73 case Z80_H: |
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74 case Z80_HL: |
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75 return Z80_L; |
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76 case Z80_IXH: |
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77 case Z80_IX: |
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78 return Z80_IXL; |
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79 case Z80_IYH: |
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80 case Z80_IY: |
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81 return Z80_IYL; |
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82 default: |
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83 return Z80_UNUSED; |
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84 } |
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85 } |
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86 |
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87 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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88 { |
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89 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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90 } |
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91 |
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92 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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93 { |
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94 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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95 uint8_t * jmp_off = dst+1; |
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96 dst = jcc(dst, CC_NC, dst + 7); |
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97 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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98 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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99 *jmp_off = dst - (jmp_off+1); |
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100 return dst; |
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101 } |
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102 |
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103 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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104 { |
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105 if (inst->reg == Z80_USE_IMMED) { |
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106 ea->mode = MODE_IMMED; |
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107 ea->disp = inst->immed; |
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108 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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109 ea->mode = MODE_UNUSED; |
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110 } else { |
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111 ea->mode = MODE_REG_DIRECT; |
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112 if (inst->reg == Z80_IYH) { |
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113 ea->base = opts->regs[Z80_IYL]; |
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114 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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115 } else if(opts->regs[inst->reg] >= 0) { |
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116 ea->base = opts->regs[inst->reg]; |
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117 if (ea->base >= AH && ea->base <= BH && (inst->addr_mode & 0x1F) == Z80_REG) { |
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118 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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119 if (other_reg > R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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120 //we can't mix an *H reg with a register that requires the REX prefix |
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121 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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122 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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123 } |
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124 } |
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125 } else { |
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126 ea->mode = MODE_REG_DISPLACE8; |
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127 ea->base = CONTEXT; |
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128 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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129 } |
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130 } |
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131 return dst; |
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132 } |
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133 |
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134 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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135 { |
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136 if (inst->reg == Z80_IYH) { |
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137 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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138 } else if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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139 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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140 if (other_reg > R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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141 //we can't mix an *H reg with a register that requires the REX prefix |
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142 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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143 } |
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144 } |
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145 return dst; |
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146 } |
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147 |
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148 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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149 { |
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150 uint8_t size, reg, areg; |
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151 ea->mode = MODE_REG_DIRECT; |
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152 areg = read ? SCRATCH1 : SCRATCH2; |
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153 switch(inst->addr_mode & 0x1F) |
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154 { |
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155 case Z80_REG: |
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156 if (inst->ea_reg == Z80_IYH) { |
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157 ea->base = opts->regs[Z80_IYL]; |
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158 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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159 } else { |
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160 ea->base = opts->regs[inst->ea_reg]; |
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161 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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162 uint8_t other_reg = opts->regs[inst->reg]; |
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163 if (other_reg > R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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164 //we can't mix an *H reg with a register that requires the REX prefix |
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165 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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166 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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167 } |
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168 } |
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169 } |
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170 break; |
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171 case Z80_REG_INDIRECT: |
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172 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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173 size = z80_size(inst); |
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174 if (read) { |
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175 if (modify) { |
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176 dst = push_r(dst, SCRATCH1); |
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177 } |
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178 if (size == SZ_B) { |
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179 dst = call(dst, (uint8_t *)z80_read_byte); |
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180 } else { |
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181 dst = call(dst, (uint8_t *)z80_read_word); |
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182 } |
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183 if (modify) { |
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184 dst = pop_r(dst, SCRATCH2); |
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185 } |
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186 } |
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187 ea->base = SCRATCH1; |
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188 break; |
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189 case Z80_IMMED: |
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190 ea->mode = MODE_IMMED; |
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191 ea->disp = inst->immed; |
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192 break; |
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193 case Z80_IMMED_INDIRECT: |
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194 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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195 size = z80_size(inst); |
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196 if (read) { |
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197 if (modify) { |
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198 dst = push_r(dst, SCRATCH1); |
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199 } |
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200 if (size == SZ_B) { |
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201 dst = call(dst, (uint8_t *)z80_read_byte); |
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202 } else { |
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203 dst = call(dst, (uint8_t *)z80_read_word); |
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204 } |
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205 if (modify) { |
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206 dst = pop_r(dst, SCRATCH2); |
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207 } |
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208 } |
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209 ea->base = SCRATCH1; |
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210 break; |
235
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211 case Z80_IX_DISPLACE: |
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212 case Z80_IY_DISPLACE: |
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213 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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214 dst = mov_rr(dst, reg, areg, SZ_W); |
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215 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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216 size = z80_size(inst); |
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217 if (read) { |
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218 if (modify) { |
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219 dst = push_r(dst, SCRATCH1); |
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220 } |
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221 if (size == SZ_B) { |
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222 dst = call(dst, (uint8_t *)z80_read_byte); |
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223 } else { |
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224 dst = call(dst, (uint8_t *)z80_read_word); |
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225 } |
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226 if (modify) { |
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227 dst = pop_r(dst, SCRATCH2); |
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228 } |
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229 } |
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230 break; |
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231 case Z80_UNUSED: |
235
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232 ea->mode = MODE_UNUSED; |
213
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233 break; |
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234 default: |
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235 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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236 exit(1); |
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237 } |
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238 return dst; |
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239 } |
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240 |
235
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241 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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242 { |
267
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243 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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244 if (inst->ea_reg == Z80_IYH) { |
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245 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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246 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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247 uint8_t other_reg = opts->regs[inst->reg]; |
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248 if (other_reg > R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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249 //we can't mix an *H reg with a register that requires the REX prefix |
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250 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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251 } |
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252 } |
213
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253 } |
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254 return dst; |
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255 } |
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256 |
235
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257 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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258 { |
253
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259 switch(inst->addr_mode & 0x1f) |
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260 { |
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261 case Z80_REG_INDIRECT: |
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262 case Z80_IMMED_INDIRECT: |
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263 case Z80_IX_DISPLACE: |
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264 case Z80_IY_DISPLACE: |
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265 if (z80_size(inst) == SZ_B) { |
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266 dst = call(dst, (uint8_t *)z80_write_byte); |
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267 } else { |
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268 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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269 } |
213
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270 } |
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271 return dst; |
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272 } |
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273 |
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274 enum { |
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275 DONT_READ=0, |
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276 READ |
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277 }; |
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278 |
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279 enum { |
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280 DONT_MODIFY=0, |
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281 MODIFY |
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282 }; |
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283 |
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284 uint8_t zf_off(uint8_t flag) |
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285 { |
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286 return offsetof(z80_context, flags) + flag; |
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287 } |
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288 |
241
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289 uint8_t zaf_off(uint8_t flag) |
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290 { |
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291 return offsetof(z80_context, alt_flags) + flag; |
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292 } |
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293 |
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294 uint8_t zar_off(uint8_t reg) |
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295 { |
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296 return offsetof(z80_context, alt_regs) + reg; |
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297 } |
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298 |
235
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299 void z80_print_regs_exit(z80_context * context) |
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300 { |
243
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301 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
235
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302 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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303 context->regs[Z80_D], context->regs[Z80_E], |
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304 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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305 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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306 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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307 context->sp, context->im, context->iff1, context->iff2); |
241
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308 puts("--Alternate Regs--"); |
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309 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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310 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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311 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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312 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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313 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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314 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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315 exit(0); |
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316 } |
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317 |
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318 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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319 { |
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320 uint32_t cycles; |
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321 x86_ea src_op, dst_op; |
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322 uint8_t size; |
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323 x86_z80_options *opts = context->options; |
261
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324 uint8_t * start = dst; |
250
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325 dst = z80_check_cycles_int(dst, address); |
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326 switch(inst->op) |
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327 { |
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328 case Z80_LD: |
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329 size = z80_size(inst); |
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330 switch (inst->addr_mode & 0x1F) |
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331 { |
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332 case Z80_REG: |
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333 case Z80_REG_INDIRECT: |
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334 cycles = size == SZ_B ? 4 : 6; |
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335 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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336 cycles += 4; |
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337 } |
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338 break; |
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339 case Z80_IMMED: |
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340 cycles = size == SZ_B ? 7 : 10; |
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341 break; |
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342 case Z80_IMMED_INDIRECT: |
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343 cycles = 10; |
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344 break; |
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345 case Z80_IX_DISPLACE: |
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346 case Z80_IY_DISPLACE: |
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347 cycles = 12; |
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348 break; |
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349 } |
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350 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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351 cycles += 4; |
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352 } |
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353 dst = zcycles(dst, cycles); |
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354 if (inst->addr_mode & Z80_DIR) { |
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355 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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356 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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357 } else { |
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358 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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359 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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360 } |
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361 if (src_op.mode == MODE_REG_DIRECT) { |
262
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362 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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363 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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364 } else { |
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365 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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366 } |
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367 } else if(src_op.mode == MODE_IMMED) { |
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368 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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369 } else { |
262
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370 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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371 } |
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372 dst = z80_save_reg(dst, inst, opts); |
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373 dst = z80_save_ea(dst, inst, opts); |
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374 if (inst->addr_mode & Z80_DIR) { |
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375 dst = z80_save_result(dst, inst); |
213
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376 } |
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377 break; |
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378 case Z80_PUSH: |
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379 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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380 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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381 if (inst->reg == Z80_AF) { |
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382 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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383 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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384 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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385 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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386 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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387 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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388 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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389 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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390 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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391 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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392 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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393 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
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394 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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395 } else { |
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396 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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397 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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398 } |
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399 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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400 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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401 //no call to save_z80_reg needed since there's no chance we'll use the only |
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402 //the upper half of a register pair |
213
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403 break; |
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404 case Z80_POP: |
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405 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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406 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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407 dst = call(dst, (uint8_t *)z80_read_word); |
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408 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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409 if (inst->reg == Z80_AF) { |
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410 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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411 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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412 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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413 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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414 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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415 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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416 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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417 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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418 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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419 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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420 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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421 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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422 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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423 } else { |
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424 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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425 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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426 } |
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427 //no call to save_z80_reg needed since there's no chance we'll use the only |
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428 //the upper half of a register pair |
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429 break; |
241
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430 case Z80_EX: |
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431 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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432 cycles = 4; |
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433 } else { |
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434 cycles = 8; |
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435 } |
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436 dst = zcycles(dst, cycles); |
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437 if (inst->addr_mode == Z80_REG) { |
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438 if(inst->reg == Z80_AF) { |
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439 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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440 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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441 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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442 |
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443 //Flags are currently word aligned, so we can move |
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444 //them efficiently a word at a time |
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445 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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446 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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447 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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448 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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449 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
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450 } |
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451 } else { |
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452 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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453 } |
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454 } else { |
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455 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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456 dst = call(dst, (uint8_t *)z80_read_byte); |
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457 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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458 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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459 dst = call(dst, (uint8_t *)z80_write_byte); |
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460 dst = zcycles(dst, 1); |
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461 uint8_t high_reg = z80_high_reg(inst->reg); |
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462 uint8_t use_reg; |
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463 //even though some of the upper halves can be used directly |
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464 //the limitations on mixing *H regs with the REX prefix |
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465 //prevent us from taking advantage of it |
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466 use_reg = opts->regs[inst->reg]; |
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467 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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468 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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469 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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470 dst = call(dst, (uint8_t *)z80_read_byte); |
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471 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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472 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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473 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
241
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474 dst = call(dst, (uint8_t *)z80_write_byte); |
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475 //restore reg to normal rotation |
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476 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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477 dst = zcycles(dst, 2); |
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478 } |
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479 break; |
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480 case Z80_EXX: |
241
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481 dst = zcycles(dst, 4); |
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482 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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483 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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484 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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485 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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486 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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487 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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488 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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489 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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490 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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491 break; |
261
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492 //case Z80_LDI: |
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493 case Z80_LDIR: { |
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494 dst = zcycles(dst, 8); |
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495 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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496 dst = call(dst, (uint8_t *)z80_read_byte); |
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497 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
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498 dst = call(dst, (uint8_t *)z80_read_byte); |
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499 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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500 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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501 |
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502 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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503 uint8_t * cont = dst+1; |
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504 dst = jcc(dst, CC_Z, dst+2); |
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505 dst = zcycles(dst, 7); |
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506 //TODO: Figure out what the flag state should be here |
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507 //TODO: Figure out whether an interrupt can interrupt this |
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508 dst = jmp(dst, start); |
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509 *cont = dst - (cont + 1); |
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510 dst = zcycles(dst, 2); |
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511 //TODO: Implement half-carry |
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512 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
513 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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514 break; |
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515 } |
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259
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|
516 /*case Z80_LDD: |
213
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|
517 case Z80_LDDR: |
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|
518 case Z80_CPI: |
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changeset
|
519 case Z80_CPIR: |
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Mike Pavone <pavone@retrodev.com>
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changeset
|
520 case Z80_CPD: |
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changeset
|
521 case Z80_CPDR: |
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changeset
|
522 break;*/ |
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Mike Pavone <pavone@retrodev.com>
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|
523 case Z80_ADD: |
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|
524 cycles = 4; |
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|
525 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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changeset
|
526 cycles += 12; |
4d4559b04c59
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|
527 } else if(inst->addr_mode == Z80_IMMED) { |
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|
528 cycles += 3; |
4d4559b04c59
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|
529 } else if(z80_size(inst) == SZ_W) { |
4d4559b04c59
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changeset
|
530 cycles += 4; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
531 } |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
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changeset
|
532 dst = zcycles(dst, cycles); |
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|
533 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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|
534 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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changeset
|
535 if (src_op.mode == MODE_REG_DIRECT) { |
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changeset
|
536 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
537 } else { |
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|
538 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
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changeset
|
539 } |
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changeset
|
540 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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|
541 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
542 //TODO: Implement half-carry flag |
4d4559b04c59
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changeset
|
543 if (z80_size(inst) == SZ_B) { |
235
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544 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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545 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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|
546 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
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changeset
|
547 } |
4d4559b04c59
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parents:
diff
changeset
|
548 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
549 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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changeset
|
550 break; |
248
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247
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changeset
|
551 case Z80_ADC: |
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552 cycles = 4; |
9c7a3db7bcd0
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553 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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247
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changeset
|
554 cycles += 12; |
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247
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changeset
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555 } else if(inst->addr_mode == Z80_IMMED) { |
9c7a3db7bcd0
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changeset
|
556 cycles += 3; |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
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557 } else if(z80_size(inst) == SZ_W) { |
9c7a3db7bcd0
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247
diff
changeset
|
558 cycles += 4; |
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Mike Pavone <pavone@retrodev.com>
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247
diff
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|
559 } |
9c7a3db7bcd0
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changeset
|
560 dst = zcycles(dst, cycles); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
561 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
9c7a3db7bcd0
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Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
562 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
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changeset
|
563 if (src_op.mode == MODE_REG_DIRECT) { |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
564 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
565 } else { |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
566 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
567 } |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
568 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
569 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
diff
changeset
|
570 //TODO: Implement half-carry flag |
9c7a3db7bcd0
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Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
571 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
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changeset
|
572 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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changeset
|
573 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
diff
changeset
|
574 dst = z80_save_reg(dst, inst, opts); |
9c7a3db7bcd0
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247
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changeset
|
575 dst = z80_save_ea(dst, inst, opts); |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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changeset
|
576 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
577 case Z80_SUB: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
578 cycles = 4; |
235
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parents:
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changeset
|
579 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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changeset
|
580 cycles += 12; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
581 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
582 cycles += 3; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
583 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
584 dst = zcycles(dst, cycles); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
585 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
586 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
587 if (src_op.mode == MODE_REG_DIRECT) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
588 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
589 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
590 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
591 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
592 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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213
diff
changeset
|
593 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
d9bf8e61c33c
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Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
594 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
595 //TODO: Implement half-carry flag |
235
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parents:
213
diff
changeset
|
596 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
597 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
598 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
599 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
600 break; |
248
9c7a3db7bcd0
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247
diff
changeset
|
601 case Z80_SBC: |
9c7a3db7bcd0
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changeset
|
602 cycles = 4; |
9c7a3db7bcd0
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247
diff
changeset
|
603 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
9c7a3db7bcd0
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changeset
|
604 cycles += 12; |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
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247
diff
changeset
|
605 } else if(inst->addr_mode == Z80_IMMED) { |
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|
606 cycles += 3; |
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|
607 } else if(z80_size(inst) == SZ_W) { |
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changeset
|
608 cycles += 4; |
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changeset
|
609 } |
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610 dst = zcycles(dst, cycles); |
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611 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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612 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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613 if (src_op.mode == MODE_REG_DIRECT) { |
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614 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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615 } else { |
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616 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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617 } |
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618 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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619 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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620 //TODO: Implement half-carry flag |
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621 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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622 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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623 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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624 dst = z80_save_reg(dst, inst, opts); |
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625 dst = z80_save_ea(dst, inst, opts); |
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626 break; |
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627 case Z80_AND: |
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628 cycles = 4; |
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629 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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630 cycles += 12; |
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631 } else if(inst->addr_mode == Z80_IMMED) { |
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632 cycles += 3; |
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633 } else if(z80_size(inst) == SZ_W) { |
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634 cycles += 4; |
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635 } |
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636 dst = zcycles(dst, cycles); |
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637 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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638 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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639 if (src_op.mode == MODE_REG_DIRECT) { |
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640 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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641 } else { |
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642 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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643 } |
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644 //TODO: Cleanup flags |
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645 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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646 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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647 //TODO: Implement half-carry flag |
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648 if (z80_size(inst) == SZ_B) { |
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649 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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650 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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651 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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652 } |
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653 dst = z80_save_reg(dst, inst, opts); |
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654 dst = z80_save_ea(dst, inst, opts); |
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655 break; |
213
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656 case Z80_OR: |
236
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657 cycles = 4; |
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658 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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659 cycles += 12; |
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660 } else if(inst->addr_mode == Z80_IMMED) { |
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661 cycles += 3; |
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662 } else if(z80_size(inst) == SZ_W) { |
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663 cycles += 4; |
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664 } |
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665 dst = zcycles(dst, cycles); |
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666 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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667 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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668 if (src_op.mode == MODE_REG_DIRECT) { |
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669 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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670 } else { |
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671 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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672 } |
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673 //TODO: Cleanup flags |
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674 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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675 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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676 //TODO: Implement half-carry flag |
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677 if (z80_size(inst) == SZ_B) { |
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678 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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679 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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680 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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681 } |
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682 dst = z80_save_reg(dst, inst, opts); |
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683 dst = z80_save_ea(dst, inst, opts); |
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684 break; |
213
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|
685 case Z80_XOR: |
236
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686 cycles = 4; |
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687 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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688 cycles += 12; |
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689 } else if(inst->addr_mode == Z80_IMMED) { |
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690 cycles += 3; |
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691 } else if(z80_size(inst) == SZ_W) { |
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692 cycles += 4; |
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693 } |
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694 dst = zcycles(dst, cycles); |
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695 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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696 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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697 if (src_op.mode == MODE_REG_DIRECT) { |
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698 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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699 } else { |
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700 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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701 } |
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702 //TODO: Cleanup flags |
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703 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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704 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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705 //TODO: Implement half-carry flag |
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706 if (z80_size(inst) == SZ_B) { |
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707 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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708 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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709 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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710 } |
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711 dst = z80_save_reg(dst, inst, opts); |
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712 dst = z80_save_ea(dst, inst, opts); |
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713 break; |
242 | 714 case Z80_CP: |
715 cycles = 4; | |
716 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
717 cycles += 12; | |
718 } else if(inst->addr_mode == Z80_IMMED) { | |
719 cycles += 3; | |
720 } | |
721 dst = zcycles(dst, cycles); | |
722 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
723 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
724 if (src_op.mode == MODE_REG_DIRECT) { | |
725 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
726 } else { | |
727 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
728 } | |
729 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
730 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
731 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
732 //TODO: Implement half-carry flag | |
733 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
734 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
735 dst = z80_save_reg(dst, inst, opts); | |
736 dst = z80_save_ea(dst, inst, opts); | |
737 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 case Z80_INC: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 cycles = 4; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 cycles += 6; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 } else if(z80_size(inst) == SZ_W) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 cycles += 2; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 cycles += 4; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 if (dst_op.mode == MODE_UNUSED) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
752 if (z80_size(inst) == SZ_B) { |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
753 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 //TODO: Implement half-carry flag |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
755 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
d9bf8e61c33c
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213
diff
changeset
|
756 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
757 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
761 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
762 case Z80_DEC: |
19fb3523a9e5
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235
diff
changeset
|
763 cycles = 4; |
19fb3523a9e5
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235
diff
changeset
|
764 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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235
diff
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|
765 cycles += 6; |
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235
diff
changeset
|
766 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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235
diff
changeset
|
767 cycles += 2; |
19fb3523a9e5
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235
diff
changeset
|
768 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
19fb3523a9e5
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235
diff
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|
769 cycles += 4; |
19fb3523a9e5
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parents:
235
diff
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|
770 } |
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235
diff
changeset
|
771 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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235
diff
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|
772 if (dst_op.mode == MODE_UNUSED) { |
19fb3523a9e5
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235
diff
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|
773 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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235
diff
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|
774 } |
19fb3523a9e5
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parents:
235
diff
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|
775 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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235
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|
776 if (z80_size(inst) == SZ_B) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
777 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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parents:
235
diff
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|
778 //TODO: Implement half-carry flag |
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Mike Pavone <pavone@retrodev.com>
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235
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changeset
|
779 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
19fb3523a9e5
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235
diff
changeset
|
780 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
diff
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|
781 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
diff
changeset
|
782 } |
19fb3523a9e5
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235
diff
changeset
|
783 dst = z80_save_reg(dst, inst, opts); |
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235
diff
changeset
|
784 dst = z80_save_ea(dst, inst, opts); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
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|
785 break; |
236
19fb3523a9e5
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235
diff
changeset
|
786 /*case Z80_DAA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
787 case Z80_CPL: |
257 | 788 case Z80_NEG:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
789 case Z80_CCF: |
257 | 790 dst = zcycles(dst, 4); |
791 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
792 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
793 //TODO: Implement half-carry flag | |
794 break; | |
795 case Z80_SCF: | |
796 dst = zcycles(dst, 4); | |
797 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
798 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
799 //TODO: Implement half-carry flag | |
800 break; | |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 case Z80_NOP: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 if (inst->immed == 42) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 break; |
243
2f069a0b487e
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Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
810 //case Z80_HALT: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
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parents:
242
diff
changeset
|
812 dst = zcycles(dst, 4); |
2f069a0b487e
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242
diff
changeset
|
813 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
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242
diff
changeset
|
814 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
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parents:
248
diff
changeset
|
815 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
2f069a0b487e
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parents:
242
diff
changeset
|
816 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 case Z80_EI: |
243
2f069a0b487e
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Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
818 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
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242
diff
changeset
|
819 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
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242
diff
changeset
|
820 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
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242
diff
changeset
|
821 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
822 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
823 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
825 dst = zcycles(dst, 4); |
2f069a0b487e
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Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
826 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
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parents:
242
diff
changeset
|
827 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
828 case Z80_RLC: |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
829 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
830 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
831 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
832 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
833 dst = zcycles(dst, 1); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
834 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
835 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
836 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
837 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
838 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
839 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
840 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
841 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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changeset
|
842 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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|
843 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
changeset
|
844 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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diff
changeset
|
845 if (inst->reg == Z80_UNUSED) { |
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diff
changeset
|
846 dst = z80_save_result(dst, inst); |
682e505f5757
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246
diff
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|
847 } else { |
682e505f5757
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246
diff
changeset
|
848 dst = z80_save_reg(dst, inst, opts); |
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246
diff
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|
849 } |
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|
850 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 case Z80_RL: |
247
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diff
changeset
|
852 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
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diff
changeset
|
853 dst = zcycles(dst, cycles); |
682e505f5757
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246
diff
changeset
|
854 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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diff
changeset
|
855 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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diff
changeset
|
856 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
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|
857 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
858 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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246
diff
changeset
|
859 } |
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changeset
|
860 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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|
861 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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changeset
|
862 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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|
863 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
changeset
|
864 //TODO: Implement half-carry flag |
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|
865 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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|
866 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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changeset
|
867 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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|
868 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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246
diff
changeset
|
869 if (inst->reg == Z80_UNUSED) { |
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246
diff
changeset
|
870 dst = z80_save_result(dst, inst); |
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246
diff
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|
871 } else { |
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246
diff
changeset
|
872 dst = z80_save_reg(dst, inst, opts); |
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246
diff
changeset
|
873 } |
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246
diff
changeset
|
874 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 case Z80_RRC: |
247
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Mike Pavone <pavone@retrodev.com>
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diff
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|
876 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
682e505f5757
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246
diff
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|
877 dst = zcycles(dst, cycles); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
878 if (inst->reg == Z80_UNUSED) { |
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246
diff
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|
879 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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246
diff
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|
880 dst = zcycles(dst, 1); |
682e505f5757
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246
diff
changeset
|
881 } else { |
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parents:
246
diff
changeset
|
882 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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246
diff
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|
883 } |
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diff
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|
884 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
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246
diff
changeset
|
885 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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diff
changeset
|
886 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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246
diff
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|
887 //TODO: Implement half-carry flag |
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246
diff
changeset
|
888 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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|
889 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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246
diff
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|
890 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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246
diff
changeset
|
891 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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246
diff
changeset
|
892 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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|
893 dst = z80_save_result(dst, inst); |
682e505f5757
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246
diff
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|
894 } else { |
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246
diff
changeset
|
895 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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246
diff
changeset
|
896 } |
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246
diff
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|
897 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 case Z80_RR: |
247
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246
diff
changeset
|
899 cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
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246
diff
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|
900 dst = zcycles(dst, cycles); |
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246
diff
changeset
|
901 if (inst->reg == Z80_UNUSED) { |
682e505f5757
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246
diff
changeset
|
902 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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246
diff
changeset
|
903 dst = zcycles(dst, 1); |
682e505f5757
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246
diff
changeset
|
904 } else { |
682e505f5757
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246
diff
changeset
|
905 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
906 } |
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246
diff
changeset
|
907 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
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246
diff
changeset
|
908 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
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246
diff
changeset
|
909 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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246
diff
changeset
|
910 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
911 //TODO: Implement half-carry flag |
682e505f5757
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246
diff
changeset
|
912 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
913 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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246
diff
changeset
|
914 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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parents:
246
diff
changeset
|
915 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
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parents:
246
diff
changeset
|
916 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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parents:
246
diff
changeset
|
917 dst = z80_save_result(dst, inst); |
682e505f5757
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parents:
246
diff
changeset
|
918 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
919 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
920 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
921 break; |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
922 /*case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 case Z80_SRA: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 case Z80_SLL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 case Z80_SRL: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 case Z80_RLD: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
927 case Z80_RRD:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 case Z80_BIT: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
929 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
930 dst = zcycles(dst, cycles); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
931 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
932 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
933 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
934 dst = zcycles(dst, 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
935 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
936 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
937 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
938 break; |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
939 case Z80_SET: |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
940 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
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parents:
246
diff
changeset
|
941 dst = zcycles(dst, cycles); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
942 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
943 if (inst->addr_mode != Z80_REG) { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
945 dst = zcycles(dst, 1); |
682e505f5757
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|
946 } |
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|
947 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
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948 if (inst->addr_mode != Z80_REG) { |
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949 dst = z80_save_result(dst, inst); |
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|
950 } |
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diff
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|
951 break; |
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|
952 case Z80_RES: |
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|
953 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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|
954 dst = zcycles(dst, cycles); |
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diff
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955 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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956 if (inst->addr_mode != Z80_REG) { |
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957 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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958 dst = zcycles(dst, 1); |
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|
959 } |
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|
960 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
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|
961 if (inst->addr_mode != Z80_REG) { |
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|
962 dst = z80_save_result(dst, inst); |
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963 } |
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|
964 break; |
236
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965 case Z80_JP: { |
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966 cycles = 4; |
239
a5bea9711a46
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|
967 if (inst->addr_mode != Z80_REG) { |
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968 cycles += 6; |
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969 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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970 cycles += 4; |
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|
971 } |
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972 dst = zcycles(dst, cycles); |
239
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238
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973 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
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974 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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975 if (!call_dst) { |
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976 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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977 //fake address to force large displacement |
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978 call_dst = dst + 256; |
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|
979 } |
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980 dst = jmp(dst, call_dst); |
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981 } else { |
239
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|
982 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
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|
983 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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984 } else { |
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|
985 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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diff
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|
986 } |
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987 dst = call(dst, (uint8_t *)z80_native_addr); |
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988 dst = jmp_r(dst, SCRATCH1); |
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|
989 } |
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|
990 break; |
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|
991 } |
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992 case Z80_JPCC: { |
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993 dst = zcycles(dst, 7);//T States: 4,3 |
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|
994 uint8_t cond = CC_Z; |
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|
995 switch (inst->reg) |
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|
996 { |
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|
997 case Z80_CC_NZ: |
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998 cond = CC_NZ; |
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999 case Z80_CC_Z: |
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1000 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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|
1001 break; |
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1002 case Z80_CC_NC: |
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|
1003 cond = CC_NZ; |
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1004 case Z80_CC_C: |
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1005 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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|
1006 break; |
238
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diff
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|
1007 case Z80_CC_PO: |
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|
1008 cond = CC_NZ; |
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|
1009 case Z80_CC_PE: |
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|
1010 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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|
1011 break; |
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|
1012 case Z80_CC_P: |
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diff
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|
1013 case Z80_CC_M: |
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diff
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|
1014 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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236
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|
1015 break; |
236
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235
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|
1016 } |
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|
1017 uint8_t *no_jump_off = dst+1; |
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|
1018 dst = jcc(dst, cond, dst+2); |
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diff
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|
1019 dst = zcycles(dst, 5);//T States: 5 |
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|
1020 uint16_t dest_addr = inst->immed; |
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|
1021 if (dest_addr < 0x4000) { |
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|
1022 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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|
1023 if (!call_dst) { |
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|
1024 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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|
1025 //fake address to force large displacement |
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|
1026 call_dst = dst + 256; |
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|
1027 } |
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|
1028 dst = jmp(dst, call_dst); |
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|
1029 } else { |
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|
1030 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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|
1031 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1032 dst = jmp_r(dst, SCRATCH1); |
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235
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|
1033 } |
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|
1034 *no_jump_off = dst - (no_jump_off+1); |
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diff
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|
1035 break; |
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|
1036 } |
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|
1037 case Z80_JR: { |
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|
1038 dst = zcycles(dst, 12);//T States: 4,3,5 |
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|
1039 uint16_t dest_addr = address + inst->immed + 2; |
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235
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|
1040 if (dest_addr < 0x4000) { |
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|
1041 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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|
1042 if (!call_dst) { |
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|
1043 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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diff
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|
1044 //fake address to force large displacement |
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|
1045 call_dst = dst + 256; |
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235
diff
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|
1046 } |
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|
1047 dst = jmp(dst, call_dst); |
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diff
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|
1048 } else { |
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diff
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|
1049 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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|
1050 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1051 dst = jmp_r(dst, SCRATCH1); |
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235
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|
1052 } |
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|
1053 break; |
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|
1054 } |
235
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213
diff
changeset
|
1055 case Z80_JRCC: { |
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|
1056 dst = zcycles(dst, 7);//T States: 4,3 |
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|
1057 uint8_t cond = CC_Z; |
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|
1058 switch (inst->reg) |
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|
1059 { |
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1060 case Z80_CC_NZ: |
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1061 cond = CC_NZ; |
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1062 case Z80_CC_Z: |
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1063 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1064 break; |
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1065 case Z80_CC_NC: |
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1066 cond = CC_NZ; |
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1067 case Z80_CC_C: |
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1068 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1069 break; |
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1070 } |
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1071 uint8_t *no_jump_off = dst+1; |
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1072 dst = jcc(dst, cond, dst+2); |
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1073 dst = zcycles(dst, 5);//T States: 5 |
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1074 uint16_t dest_addr = address + inst->immed + 2; |
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1075 if (dest_addr < 0x4000) { |
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1076 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1077 if (!call_dst) { |
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1078 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1079 //fake address to force large displacement |
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1080 call_dst = dst + 256; |
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1081 } |
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1082 dst = jmp(dst, call_dst); |
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1083 } else { |
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1084 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1085 dst = call(dst, (uint8_t *)z80_native_addr); |
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1086 dst = jmp_r(dst, SCRATCH1); |
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1087 } |
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1088 *no_jump_off = dst - (no_jump_off+1); |
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1089 break; |
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1090 } |
239
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1091 case Z80_DJNZ: |
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1092 dst = zcycles(dst, 8);//T States: 5,3 |
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1093 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
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1094 uint8_t *no_jump_off = dst+1; |
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1095 dst = jcc(dst, CC_Z, dst+2); |
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1096 dst = zcycles(dst, 5);//T States: 5 |
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1097 uint16_t dest_addr = address + inst->immed + 2; |
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1098 if (dest_addr < 0x4000) { |
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1099 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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1100 if (!call_dst) { |
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1101 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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1102 //fake address to force large displacement |
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1103 call_dst = dst + 256; |
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1104 } |
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1105 dst = jmp(dst, call_dst); |
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1106 } else { |
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1107 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1108 dst = call(dst, (uint8_t *)z80_native_addr); |
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1109 dst = jmp_r(dst, SCRATCH1); |
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1110 } |
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1111 *no_jump_off = dst - (no_jump_off+1); |
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1112 break; |
235
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1113 case Z80_CALL: { |
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1114 dst = zcycles(dst, 11);//T States: 4,3,4 |
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1115 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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1116 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
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1117 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
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1118 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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1119 if (inst->immed < 0x4000) { |
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1120 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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1121 if (!call_dst) { |
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1122 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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1123 //fake address to force large displacement |
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1124 call_dst = dst + 256; |
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1125 } |
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1126 dst = jmp(dst, call_dst); |
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1127 } else { |
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1128 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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1129 dst = call(dst, (uint8_t *)z80_native_addr); |
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1130 dst = jmp_r(dst, SCRATCH1); |
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1131 } |
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1132 break; |
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|
1133 } |
238
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1134 case Z80_CALLCC: |
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1135 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
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1136 uint8_t cond = CC_Z; |
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1137 switch (inst->reg) |
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1138 { |
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|
1139 case Z80_CC_NZ: |
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1140 cond = CC_NZ; |
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1141 case Z80_CC_Z: |
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1142 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1143 break; |
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|
1144 case Z80_CC_NC: |
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1145 cond = CC_NZ; |
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1146 case Z80_CC_C: |
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1147 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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1148 break; |
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1149 case Z80_CC_PO: |
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1150 cond = CC_NZ; |
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1151 case Z80_CC_PE: |
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1152 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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|
1153 break; |
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|
1154 case Z80_CC_P: |
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1155 case Z80_CC_M: |
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1156 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
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|
1157 break; |
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1158 } |
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|
1159 uint8_t *no_call_off = dst+1; |
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1160 dst = jcc(dst, cond, dst+2); |
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1161 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
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|
1162 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
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|
1163 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
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1164 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
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1165 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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|
1166 if (inst->immed < 0x4000) { |
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|
1167 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
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236
diff
changeset
|
1168 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
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|
1169 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
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236
diff
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|
1170 //fake address to force large displacement |
827ebce557bf
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236
diff
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|
1171 call_dst = dst + 256; |
827ebce557bf
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236
diff
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|
1172 } |
827ebce557bf
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236
diff
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|
1173 dst = jmp(dst, call_dst); |
827ebce557bf
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236
diff
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|
1174 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
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|
1175 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
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236
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|
1176 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
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236
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|
1177 dst = jmp_r(dst, SCRATCH1); |
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|
1178 } |
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236
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|
1179 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
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236
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|
1180 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
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|
1181 case Z80_RET: |
235
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213
diff
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|
1182 dst = zcycles(dst, 4);//T States: 4 |
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Get Z80 core working for simple programs
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|
1183 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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|
1184 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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Get Z80 core working for simple programs
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|
1185 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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Get Z80 core working for simple programs
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|
1186 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1187 dst = jmp_r(dst, SCRATCH1); |
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|
1188 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
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|
1189 case Z80_RETCC: { |
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Implement RETCC in Z80 core.
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243
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|
1190 dst = zcycles(dst, 5);//T States: 5 |
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Implement RETCC in Z80 core.
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|
1191 uint8_t cond = CC_Z; |
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Implement RETCC in Z80 core.
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diff
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|
1192 switch (inst->reg) |
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Implement RETCC in Z80 core.
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243
diff
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|
1193 { |
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Implement RETCC in Z80 core.
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243
diff
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|
1194 case Z80_CC_NZ: |
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Implement RETCC in Z80 core.
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243
diff
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|
1195 cond = CC_NZ; |
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Implement RETCC in Z80 core.
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|
1196 case Z80_CC_Z: |
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Implement RETCC in Z80 core.
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243
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|
1197 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Implement RETCC in Z80 core.
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|
1198 break; |
ed548c77b598
Implement RETCC in Z80 core.
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diff
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|
1199 case Z80_CC_NC: |
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Implement RETCC in Z80 core.
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243
diff
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|
1200 cond = CC_NZ; |
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Implement RETCC in Z80 core.
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243
diff
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|
1201 case Z80_CC_C: |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1202 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
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|
1203 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
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|
1204 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1205 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1206 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1207 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1208 break; |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1209 case Z80_CC_P: |
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Implement RETCC in Z80 core.
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243
diff
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|
1210 case Z80_CC_M: |
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Implement RETCC in Z80 core.
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243
diff
changeset
|
1211 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
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243
diff
changeset
|
1212 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1213 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1214 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1215 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1216 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
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243
diff
changeset
|
1217 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
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Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1218 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1219 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
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parents:
243
diff
changeset
|
1220 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1221 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1222 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1223 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1224 /*case Z80_RETI: |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1225 case Z80_RETN:*/ |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1226 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
1227 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1228 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1229 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1230 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1231 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1232 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1233 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1234 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1235 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1236 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1237 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1238 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1239 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1240 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1241 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1242 /*case Z80_IN: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1243 case Z80_INI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1244 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1245 case Z80_IND: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1246 case Z80_INDR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1247 case Z80_OUT: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1248 case Z80_OUTI: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1249 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1250 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1251 case Z80_OTDR:*/ |
235
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parents:
213
diff
changeset
|
1252 default: { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1253 char disbuf[80]; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1254 z80_disasm(inst, disbuf); |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1255 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1256 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1257 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
1258 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1259 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1260 } |
235
d9bf8e61c33c
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parents:
213
diff
changeset
|
1261 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1262 return dst; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1263 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1264 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1265 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1266 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1267 native_map_slot *map; |
d9bf8e61c33c
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213
diff
changeset
|
1268 if (address < 0x4000) { |
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213
diff
changeset
|
1269 address &= 0x1FFF; |
d9bf8e61c33c
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213
diff
changeset
|
1270 map = context->static_code_map; |
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213
diff
changeset
|
1271 } else if (address >= 0x8000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1272 address &= 0x7FFF; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1273 map = context->banked_code_map + (context->bank_reg << 15); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1274 } else { |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1275 printf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1276 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1277 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1278 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET) { |
267
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1279 printf("z80_get_native_address: %X NULL\n", address); |
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1280 return NULL; |
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1281 } |
267
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1282 printf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
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1283 return map->base + map->offsets[address]; |
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1284 } |
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1285 |
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1286 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
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1287 { |
252
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1288 if (address >= 0x4000) { |
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1289 return 0; |
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1290 } |
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1291 return opts->ram_inst_sizes[address & 0x1FFF]; |
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|
1292 } |
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1293 |
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1294 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
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1295 { |
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1296 uint32_t orig_address = address; |
235
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1297 native_map_slot *map; |
252
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|
1298 x86_z80_options * opts = context->options; |
235
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1299 if (address < 0x4000) { |
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1300 address &= 0x1FFF; |
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1301 map = context->static_code_map; |
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|
1302 opts->ram_inst_sizes[address] = native_size; |
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1303 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
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1304 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
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1305 } else if (address >= 0x8000) { |
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1306 address &= 0x7FFF; |
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1307 map = context->banked_code_map + (context->bank_reg << 15); |
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1308 if (!map->offsets) { |
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1309 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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1310 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1311 } |
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|
1312 } else { |
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|
1313 return; |
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1314 } |
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1315 if (!map->base) { |
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1316 map->base = native_address; |
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1317 } |
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|
1318 map->offsets[address] = native_address - map->base; |
253
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1319 for(--size, orig_address++; size; --size, orig_address++) { |
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1320 address = orig_address; |
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1321 if (address < 0x4000) { |
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1322 address &= 0x1FFF; |
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1323 map = context->static_code_map; |
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1324 } else if (address >= 0x8000) { |
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|
1325 address &= 0x7FFF; |
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1326 map = context->banked_code_map + (context->bank_reg << 15); |
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1327 } else { |
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1328 return; |
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1329 } |
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1330 if (!map->offsets) { |
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1331 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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|
1332 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1333 } |
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1334 map->offsets[address] = EXTENSION_WORD; |
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1335 } |
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1336 } |
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1337 |
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|
1338 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
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1339 |
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1340 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
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1341 { |
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|
1342 if (!static_code_map->base || address >= 0x4000) { |
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|
1343 return INVALID_INSTRUCTION_START; |
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1344 } |
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|
1345 address &= 0x1FFF; |
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|
1346 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
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|
1347 return INVALID_INSTRUCTION_START; |
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1348 } |
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|
1349 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
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1350 --address; |
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|
1351 address &= 0x1FFF; |
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1352 } |
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1353 return address; |
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1354 } |
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1355 |
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1356 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
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1357 { |
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1358 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
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1359 if (inst_start != INVALID_INSTRUCTION_START) { |
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1360 uint8_t * dst = z80_get_native_address(context, inst_start); |
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1361 printf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
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1362 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
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1363 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
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1364 } |
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1365 return context; |
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1366 } |
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1367 |
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1368 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
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1369 { |
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1370 uint8_t * addr = z80_get_native_address(context, address); |
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1371 if (!addr) { |
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1372 translate_z80_stream(context, address); |
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1373 addr = z80_get_native_address(context, address); |
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1374 if (!addr) { |
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1375 printf("Failed to translate %X to native code\n", address); |
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1376 } |
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|
1377 } |
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|
1378 return addr; |
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1379 } |
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1380 |
266
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|
1381 void z80_handle_deferred(z80_context * context) |
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|
1382 { |
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|
1383 x86_z80_options * opts = context->options; |
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1384 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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|
1385 if (opts->deferred) { |
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diff
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|
1386 translate_z80_stream(context, opts->deferred->address); |
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diff
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|
1387 } |
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264
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|
1388 } |
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|
1389 |
252
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diff
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|
1390 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
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|
1391 { |
266
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|
1392 char disbuf[80]; |
252
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|
1393 x86_z80_options * opts = context->options; |
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|
1394 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
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|
1395 uint8_t * orig_start = z80_get_native_address(context, address); |
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|
1396 uint32_t orig = address; |
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|
1397 address &= 0x1FFF; |
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|
1398 uint8_t * dst = opts->cur_code; |
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|
1399 uint8_t * dst_end = opts->code_end; |
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|
1400 uint8_t *after, *inst = context->mem_pointers[0] + address; |
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|
1401 z80inst instbuf; |
267
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|
1402 printf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
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diff
changeset
|
1403 after = z80_decode(inst, &instbuf); |
267
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266
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|
1404 z80_disasm(&instbuf, disbuf); |
266
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264
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|
1405 if (instbuf.op == Z80_NOP) { |
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264
diff
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|
1406 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
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264
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|
1407 } else { |
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264
diff
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|
1408 printf("%X\t%s\n", address, disbuf); |
267
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Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
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266
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|
1409 } |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1410 if (orig_size != ZMAX_NATIVE_SIZE) { |
63b9a500a00b
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250
diff
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|
1411 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1412 size_t size = 1024*1024; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1413 dst = alloc_code(&size); |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
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|
1414 opts->code_end = dst_end = dst + size; |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1415 opts->cur_code = dst; |
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Mike Pavone <pavone@retrodev.com>
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250
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|
1416 } |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
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|
1417 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1418 if ((native_end - dst) <= orig_size) { |
264
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Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1419 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1420 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1421 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
266
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Mike Pavone <pavone@retrodev.com>
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264
diff
changeset
|
1422 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1423 while (native_end < orig_start + orig_size) { |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
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|
1424 *(native_end++) = 0x90; //NOP |
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Fix a crash bug in instruction retranslation
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262
diff
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|
1425 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1426 } else { |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1427 jmp(native_end, native_next); |
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1428 } |
266
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parents:
264
diff
changeset
|
1429 z80_handle_deferred(context); |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
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|
1430 return orig_start; |
252
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diff
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|
1431 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
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|
1432 } |
264
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Fix a crash bug in instruction retranslation
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262
diff
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|
1433 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
266
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264
diff
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|
1434 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
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Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
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264
diff
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|
1435 jmp(orig_start, dst); |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1436 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) { |
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Fix a crash bug in instruction retranslation
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262
diff
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|
1437 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
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Fix a crash bug in instruction retranslation
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262
diff
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|
1438 } |
266
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264
diff
changeset
|
1439 z80_handle_deferred(context); |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1440 return dst; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
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|
1441 } else { |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1442 dst = translate_z80inst(&instbuf, orig_start, context, address); |
254
64feb6b67244
Fix bug in end condition inside translate_z80_stream.
Mike Pavone <pavone@retrodev.com>
parents:
253
diff
changeset
|
1443 if(!(instbuf.op == Z80_RET || instbuf.op == Z80_RETI || instbuf.op == Z80_RETN || instbuf.op == Z80_JP || (instbuf.op == Z80_NOP && instbuf.immed == 42))) { |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
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|
1444 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
252
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250
diff
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|
1445 } |
266
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Fix some more retranslation bugs in the Z80 core
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264
diff
changeset
|
1446 z80_handle_deferred(context); |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1447 return orig_start; |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1448 } |
235
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213
diff
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|
1449 } |
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213
diff
changeset
|
1450 |
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diff
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|
1451 void translate_z80_stream(z80_context * context, uint32_t address) |
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213
diff
changeset
|
1452 { |
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213
diff
changeset
|
1453 char disbuf[80]; |
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Get Z80 core working for simple programs
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213
diff
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|
1454 if (z80_get_native_address(context, address)) { |
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213
diff
changeset
|
1455 return; |
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213
diff
changeset
|
1456 } |
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213
diff
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|
1457 x86_z80_options * opts = context->options; |
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Get Z80 core working for simple programs
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213
diff
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|
1458 uint8_t * encoded = NULL, *next; |
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Get Z80 core working for simple programs
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213
diff
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|
1459 if (address < 0x4000) { |
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Get Z80 core working for simple programs
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213
diff
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|
1460 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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Get Z80 core working for simple programs
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213
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|
1461 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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|
1462 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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|
1463 } |
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|
1464 while (encoded != NULL) |
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213
diff
changeset
|
1465 { |
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213
diff
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|
1466 z80inst inst; |
267
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Don't mix *H regs with the REX prefix
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266
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|
1467 printf("translating Z80 code at address %X\n", address); |
235
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|
1468 do { |
252
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|
1469 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
235
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|
1470 if (opts->code_end-opts->cur_code < 5) { |
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|
1471 puts("out of code memory, not enough space for jmp to next chunk"); |
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changeset
|
1472 exit(1); |
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diff
changeset
|
1473 } |
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|
1474 size_t size = 1024*1024; |
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|
1475 opts->cur_code = alloc_code(&size); |
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|
1476 opts->code_end = opts->cur_code + size; |
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|
1477 jmp(opts->cur_code, opts->cur_code); |
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|
1478 } |
255
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254
diff
changeset
|
1479 if (address > 0x4000 && address < 0x8000) { |
235
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|
1480 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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|
1481 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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changeset
|
1482 break; |
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|
1483 } |
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|
1484 uint8_t * existing = z80_get_native_address(context, address); |
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|
1485 if (existing) { |
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1486 opts->cur_code = jmp(opts->cur_code, existing); |
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1487 break; |
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1488 } |
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1489 next = z80_decode(encoded, &inst); |
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1490 z80_disasm(&inst, disbuf); |
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1491 if (inst.op == Z80_NOP) { |
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1492 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1493 } else { |
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1494 printf("%X\t%s\n", address, disbuf); |
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1495 } |
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1496 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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1497 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
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1498 opts->cur_code = after; |
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1499 address += next-encoded; |
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1500 if (address > 0xFFFF) { |
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1501 address &= 0xFFFF; |
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1502 |
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1503 } else { |
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1504 encoded = next; |
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1505 } |
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1506 } while (!(inst.op == Z80_RET || inst.op == Z80_RETI || inst.op == Z80_RETN || inst.op == Z80_JP || (inst.op == Z80_NOP && inst.immed == 42))); |
235
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1507 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1508 if (opts->deferred) { |
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1509 address = opts->deferred->address; |
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1510 printf("defferred address: %X\n", address); |
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1511 if (address < 0x4000) { |
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1512 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1513 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1514 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1515 } else { |
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1516 printf("attempt to translate non-memory address: %X\n", address); |
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1517 exit(1); |
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1518 } |
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1519 } else { |
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1520 encoded = NULL; |
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1521 } |
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1522 } |
213
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1523 } |
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1524 |
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1525 void init_x86_z80_opts(x86_z80_options * options) |
213
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1526 { |
235
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1527 options->flags = 0; |
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1528 options->regs[Z80_B] = BH; |
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1529 options->regs[Z80_C] = RBX; |
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1530 options->regs[Z80_D] = CH; |
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1531 options->regs[Z80_E] = RCX; |
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1532 options->regs[Z80_H] = AH; |
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1533 options->regs[Z80_L] = RAX; |
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1534 options->regs[Z80_IXH] = DH; |
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1535 options->regs[Z80_IXL] = RDX; |
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1536 options->regs[Z80_IYH] = -1; |
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1537 options->regs[Z80_IYL] = R8; |
235
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1538 options->regs[Z80_I] = -1; |
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1539 options->regs[Z80_R] = -1; |
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1540 options->regs[Z80_A] = R10; |
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1541 options->regs[Z80_BC] = RBX; |
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1542 options->regs[Z80_DE] = RCX; |
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1543 options->regs[Z80_HL] = RAX; |
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1544 options->regs[Z80_SP] = R9; |
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1545 options->regs[Z80_AF] = -1; |
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1546 options->regs[Z80_IX] = RDX; |
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1547 options->regs[Z80_IY] = R8; |
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1548 size_t size = 1024 * 1024; |
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1549 options->cur_code = alloc_code(&size); |
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1550 options->code_end = options->cur_code + size; |
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1551 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1552 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
235
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1553 options->deferred = NULL; |
213
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1554 } |
235
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1555 |
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1556 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1557 { |
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1558 memset(context, 0, sizeof(*context)); |
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1559 context->static_code_map = malloc(sizeof(context->static_code_map)); |
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1560 context->static_code_map->base = NULL; |
235
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1561 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1562 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1563 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1564 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
235
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1565 context->options = options; |
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1566 } |
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1567 |
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1568 void z80_reset(z80_context * context) |
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1569 { |
259
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1570 context->im = 0; |
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1571 context->iff1 = context->iff2 = 0; |
235
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1572 context->native_pc = z80_get_native_address_trans(context, 0); |
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1573 } |
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1574 |
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1575 |