Mercurial > repos > blastem
annotate cpu_dsl.py @ 1754:043cf458704c
Basic support for string operands in CPU DSL
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Fri, 15 Feb 2019 23:58:34 -0800 |
parents | 33ec5df77fac |
children | 6e4faa10f9ee |
rev | line source |
---|---|
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1 #!/usr/bin/env python3 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4 class Block: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
5 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
6 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
7 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
8 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
9 if parts[0] == 'switch': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
10 o = Switch(self, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
11 self.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
12 return o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
13 elif parts[0] == 'if': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
14 o = If(self, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
15 self.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
16 return o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
17 elif parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
18 raise Exception('end is only allowed inside a switch or if block') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
19 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
20 self.addOp(NormalOp(parts)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
21 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
22 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
23 def processOps(self, prog, fieldVals, output, otype, oplist): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
24 for i in range(0, len(oplist)): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
25 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags': |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
26 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0]) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
27 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
28 flagUpdates = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
29 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
30 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
31 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
32 return None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
33 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
34 class ChildBlock(Block): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
35 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
36 if parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
37 return self.parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
38 return super().processLine(parts) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
39 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
40 #Represents an instruction of the emulated CPU |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
41 class Instruction(Block): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
42 def __init__(self, value, fields, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
43 self.value = value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
44 self.fields = fields |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
45 self.name = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
46 self.implementation = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
47 self.locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
48 self.regValues = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
49 self.varyingBits = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
50 self.invalidFieldValues = {} |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
51 self.newLocals = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
52 for field in fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
53 self.varyingBits += fields[field][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
54 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
55 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
56 if op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
57 name = op.params[0] |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
58 size = int(op.params[1]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
59 self.locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
60 elif op.op == 'invalid': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
61 name = op.params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
62 value = int(op.params[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
63 self.invalidFieldValues.setdefault(name, set()).add(value) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
64 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
65 self.implementation.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
66 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
67 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
68 if name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
69 return name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
70 return None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
71 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
72 def addLocal(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
73 self.locals[name] = size |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
74 self.newLocals.append(name) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
75 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
76 def localSize(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
77 return self.locals.get(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
78 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
79 def __lt__(self, other): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
80 if isinstance(other, Instruction): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
81 if self.varyingBits != other.varyingBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
82 return self.varyingBits < other.varyingBits |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
83 return self.value < other.value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
84 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
85 return NotImplemented |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
86 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
87 def allValues(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
88 values = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
89 for i in range(0, 1 << self.varyingBits): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
90 iword = self.value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
91 doIt = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
92 for field in self.fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
93 shift,bits = self.fields[field] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
94 val = i & ((1 << bits) - 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
95 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
96 doIt = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
97 break |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
98 i >>= bits |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
99 iword |= val << shift |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
100 if doIt: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
101 values.append(iword) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
102 return values |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
103 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
104 def getFieldVals(self, value): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
105 fieldVals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
106 fieldBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
107 for field in self.fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
108 shift,bits = self.fields[field] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
109 val = (value >> shift) & ((1 << bits) - 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
110 fieldVals[field] = val |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
111 fieldBits[field] = bits |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
112 return (fieldVals, fieldBits) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
113 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
114 def generateName(self, value): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
115 fieldVals,fieldBits = self.getFieldVals(value) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
116 names = list(fieldVals.keys()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
117 names.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
118 funName = self.name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
119 for name in names: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
120 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
121 return funName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
122 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
123 def generateBody(self, value, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
124 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
125 prog.meta = {} |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
126 prog.pushScope(self) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
127 self.regValues = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
128 for var in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
129 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
130 self.newLocals = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
131 fieldVals,_ = self.getFieldVals(value) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
132 self.processOps(prog, fieldVals, output, otype, self.implementation) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
133 |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
134 if prog.dispatch == 'call': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
135 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context)\n{' |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
136 elif prog.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
137 begin = '\n' + self.generateName(value) + ': {' |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
138 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
139 raise Exception('Unsupported dispatch type ' + prog.dispatch) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
140 if prog.needFlagCoalesce: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
141 begin += prog.flags.coalesceFlags(prog, otype) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
142 if prog.needFlagDisperse: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
143 output.append(prog.flags.disperseFlags(prog, otype)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
144 for var in self.newLocals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
145 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
146 prog.popScope() |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
147 if prog.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
148 output += prog.nextInstruction(otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
149 return begin + ''.join(output) + '\n}' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
150 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
151 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
152 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
153 for name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
154 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
155 for op in self.implementation: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
156 pieces.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
157 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
158 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
159 #Represents the definition of a helper function |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
160 class SubRoutine(Block): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
161 def __init__(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
162 self.name = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
163 self.implementation = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
164 self.args = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
165 self.arg_map = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
166 self.locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
167 self.regValues = {} |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
168 self.argValues = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
169 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
170 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
171 if op.op == 'arg': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
172 name = op.params[0] |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
173 size = int(op.params[1]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
174 self.arg_map[name] = len(self.args) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
175 self.args.append((name, size)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
176 elif op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
177 name = op.params[0] |
1734
88fbc4e711fd
Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1733
diff
changeset
|
178 size = int(op.params[1]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
179 self.locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
180 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
181 self.implementation.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
182 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
183 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
184 if name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
185 return self.name + '_' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
186 return None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
187 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
188 def addLocal(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
189 self.locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
190 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
191 def localSize(self, name): |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
192 if name in self.locals: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
193 return self.locals[name] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
194 if name in self.arg_map: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
195 argIndex = self.arg_map[name] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
196 return self.args[argIndex][1] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
197 return None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
198 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
199 def inline(self, prog, params, output, otype, parent): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
200 if len(params) != len(self.args): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
201 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
202 argValues = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
203 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
204 self.regValues = parent.regValues |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
205 prog.pushScope(self) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
206 i = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
207 for name,size in self.args: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
208 argValues[name] = params[i] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
209 i += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
210 for name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
211 size = self.locals[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
212 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name)) |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
213 self.argValues = argValues |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
214 self.processOps(prog, argValues, output, otype, self.implementation) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
215 prog.popScope() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
216 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
217 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
218 pieces = [self.name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
219 for name,size in self.args: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
220 pieces.append('\n\targ {0} {1}'.format(name, size)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
221 for name in self.locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
222 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
223 for op in self.implementation: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
224 pieces.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
225 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
226 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
227 class Op: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
228 def __init__(self, evalFun = None): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
229 self.evalFun = evalFun |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
230 self.impls = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
231 self.outOp = () |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
232 def cBinaryOperator(self, op): |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
233 def _impl(prog, params, rawParams, flagUpdates): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
234 if op == '-': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
235 a = params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
236 b = params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
237 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
238 a = params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
239 b = params[1] |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
240 needsCarry = needsOflow = needsHalf = False |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
241 if flagUpdates: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
242 for flag in flagUpdates: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
243 calc = prog.flags.flagCalc[flag] |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
244 if calc == 'carry': |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
245 needsCarry = True |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
246 elif calc == 'half-carry': |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
247 needsHalf = True |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
248 elif calc == 'overflow': |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
249 needsOflow = True |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
250 decl = '' |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
251 if needsCarry or needsOflow or needsHalf: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
252 size = prog.paramSize(rawParams[2]) |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
253 if needsCarry and op != 'lsr': |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
254 size *= 2 |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
255 decl,name = prog.getTemp(size) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
256 dst = prog.carryFlowDst = name |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
257 prog.lastA = a |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
258 prog.lastB = b |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
259 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
260 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
261 dst = params[2] |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
262 return decl + '\n\t{dst} = {a} {op} {b};'.format( |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
263 dst = dst, a = a, b = b, op = op |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
264 ) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
265 self.impls['c'] = _impl |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
266 self.outOp = (2,) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
267 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
268 def cUnaryOperator(self, op): |
1725
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
269 def _impl(prog, params, rawParams, flagUpdates): |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
270 dst = params[1] |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
271 decl = '' |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
272 if op == '-': |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
273 if flagUpdates: |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
274 for flag in flagUpdates: |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
275 calc = prog.flags.flagCalc[flag] |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
276 if calc == 'carry': |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
277 needsCarry = True |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
278 elif calc == 'half-carry': |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
279 needsHalf = True |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
280 elif calc == 'overflow': |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
281 needsOflow = True |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
282 if needsCarry or needsOflow or needsHalf: |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
283 size = prog.paramSize(rawParams[1]) |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
284 if needsCarry: |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
285 size *= 2 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
286 decl,name = prog.getTemp(size) |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
287 dst = prog.carryFlowDst = name |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
288 prog.lastA = 0 |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
289 prog.lastB = params[0] |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
290 prog.lastBFlow = params[0] |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
291 return decl + '\n\t{dst} = {op}{a};'.format( |
89ee53a149ea
Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1723
diff
changeset
|
292 dst = dst, a = params[0], op = op |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
293 ) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
294 self.impls['c'] = _impl |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
295 self.outOp = (1,) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
296 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
297 def addImplementation(self, lang, outOp, impl): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
298 self.impls[lang] = impl |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
299 if not outOp is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
300 if type(outOp) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
301 self.outOp = outOp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
302 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
303 self.outOp = (outOp,) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
304 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
305 def evaluate(self, params): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
306 return self.evalFun(*params) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
307 def canEval(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
308 return not self.evalFun is None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
309 def numArgs(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
310 return self.evalFun.__code__.co_argcount |
1716
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
311 def numParams(self): |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
312 if self.outOp: |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
313 params = max(self.outOp) + 1 |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
314 else: |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
315 params = 0 |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
316 if self.evalFun: |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
317 params = max(params, self.numArgs()) |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
318 return params |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
319 def generate(self, otype, prog, params, rawParams, flagUpdates): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
320 if self.impls[otype].__code__.co_argcount == 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
321 return self.impls[otype](prog, params) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
322 elif self.impls[otype].__code__.co_argcount == 3: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
323 return self.impls[otype](prog, params, rawParams) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
324 else: |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
325 return self.impls[otype](prog, params, rawParams, flagUpdates) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
326 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
327 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
328 def _xchgCImpl(prog, params, rawParams): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
329 size = prog.paramSize(rawParams[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
330 decl,name = prog.getTemp(size) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
331 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
332 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
333 def _dispatchCImpl(prog, params): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
334 if len(params) == 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
335 table = 'main' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
336 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
337 table = params[1] |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
338 if prog.dispatch == 'call': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
339 return '\n\timpl_{tbl}[{op}](context);'.format(tbl = table, op = params[0]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
340 elif prog.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
341 return '\n\tgoto *impl_{tbl}[{op}];'.format(tbl = table, op = params[0]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
342 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
343 raise Exception('Unsupported dispatch type ' + prog.dispatch) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
344 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
345 def _updateFlagsCImpl(prog, params, rawParams): |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
346 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
347 output = [] |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
348 parity = None |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
349 directFlags = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
350 for flag in autoUpdate: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
351 calc = prog.flags.flagCalc[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
352 calc,_,resultBit = calc.partition('-') |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
353 if prog.carryFlowDst: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
354 lastDst = prog.carryFlowDst |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
355 else: |
1734
88fbc4e711fd
Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1733
diff
changeset
|
356 lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {}) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
357 storage = prog.flags.getStorage(flag) |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
358 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow': |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
359 myRes = lastDst |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
360 if calc == 'sign': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
361 resultBit = prog.paramSize(prog.lastDst) - 1 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
362 elif calc == 'carry': |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
363 if prog.lastOp.op in ('asr', 'lsr'): |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
364 resultBit = 0 |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
365 myRes = prog.lastA |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
366 else: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
367 resultBit = prog.paramSize(prog.lastDst) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
368 if prog.lastOp.op == 'ror': |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
369 resultBit -= 1 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
370 elif calc == 'half': |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
371 resultBit = prog.paramSize(prog.lastDst) - 4 |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
372 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst) |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
373 elif calc == 'overflow': |
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
374 resultBit = prog.paramSize(prog.lastDst) - 1 |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
375 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
376 else: |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
377 #Note: offsetting this by the operation size - 8 makes sense for the Z80 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
378 #but might not for other CPUs with this kind of fixed bit flag behavior |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
379 resultBit = int(resultBit) + prog.paramSize(prog.lastDst) - 8 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 if type(storage) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
381 reg,storageBit = storage |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 if storageBit == resultBit: |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
383 directFlags.setdefault((reg, myRes), []).append(resultBit) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
384 else: |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
385 reg = prog.resolveParam(reg, None, {}) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
386 if resultBit > storageBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
387 op = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 shift = resultBit - storageBit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 op = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 shift = storageBit - resultBit |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
392 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} {op} {shift}U & {mask}U);'.format( |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
393 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
394 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
395 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
396 reg = prog.resolveParam(storage, None, {}) |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
397 maxBit = prog.paramSize(storage) - 1 |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
398 if resultBit > maxBit: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
399 output.append('\n\t{reg} = {res} >> {shift} & {mask}U;'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = 1 << maxBit)) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
400 else: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
401 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
402 elif calc == 'zero': |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
403 if prog.carryFlowDst: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
404 realSize = prog.paramSize(prog.lastDst) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
405 if realSize != prog.paramSize(prog.carryFlowDst): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
406 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
407 if type(storage) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
408 reg,storageBit = storage |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
409 reg = prog.resolveParam(reg, None, {}) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
410 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 )) |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
413 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
414 reg = prog.resolveParam(storage, None, {}) |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
415 output.append('\n\t{reg} = {res} == 0;'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 reg = reg, res = lastDst |
1705
9ab64ef5cba0
Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Michael Pavone <pavone@retrodev.com>
parents:
1704
diff
changeset
|
417 )) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 elif calc == 'parity': |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
419 parity = storage |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
420 paritySize = prog.paramSize(prog.lastDst) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
421 if prog.carryFlowDst: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
422 parityDst = paritySrc = prog.carryFlowDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
423 else: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
424 paritySrc = lastDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
425 decl,name = prog.getTemp(paritySize) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
426 output.append(decl) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
427 parityDst = name |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
428 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
429 raise Exception('Unknown flag calc type: ' + calc) |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
430 for reg, myRes in directFlags: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
431 bits = directFlags[(reg, myRes)] |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
432 resolved = prog.resolveParam(reg, None, {}) |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
433 if len(bits) == len(prog.flags.storageToFlags[reg]): |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
434 output.append('\n\t{reg} = {res};'.format(reg = resolved, res = myRes)) |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
435 else: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
436 mask = 0 |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
437 for bit in bits: |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
438 mask |= 1 << bit |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
439 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} & {mask}U);'.format( |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
440 reg = resolved, mask = mask, res = myRes |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
441 )) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
442 if prog.carryFlowDst: |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
443 if prog.lastOp.op != 'cmp': |
1742
6290c88949bd
Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1740
diff
changeset
|
444 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
445 prog.carryFlowDst = None |
1713
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
446 if parity: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
447 if paritySize > 8: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
448 if paritySize > 16: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
449 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
450 paritySrc = parityDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
451 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
452 paritySrc = parityDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
453 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
454 if type(parity) is tuple: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
455 reg,bit = parity |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
456 reg = prog.resolveParam(reg, None, {}) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
457 output.append('\n\t{flag} = ({flag} & ~{mask}U) | ((0x6996 >> {parity}) << {bit} & {mask}U);'.format( |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
458 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
459 )) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
460 else: |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
461 reg = prog.resolveParam(parity, None, {}) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
462 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst)) |
0264d8b288e2
Implement parity flag calculation type
Michael Pavone <pavone@retrodev.com>
parents:
1711
diff
changeset
|
463 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
464 #TODO: combine explicit flags targeting the same storage location |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 for flag in explicit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 location = prog.flags.getStorage(flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 if type(location) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 reg,bit = location |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
469 reg = prog.resolveReg(reg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 value = str(1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 if explicit[flag]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 operator = '|=' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
473 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 operator = '&=' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 value = '~' + value |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
476 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
477 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
478 reg = prog.resolveReg(location, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
480 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
481 |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
482 def _cmpCImpl(prog, params, rawParams, flagUpdates): |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
483 size = prog.paramSize(rawParams[1]) |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
484 needsCarry = False |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
485 if flagUpdates: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
486 for flag in flagUpdates: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
487 calc = prog.flags.flagCalc[flag] |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
488 if calc == 'carry': |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
489 needsCarry = True |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
490 break |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
491 if needsCarry: |
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
492 size *= 2 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 tmpvar = 'cmp_tmp{sz}__'.format(sz=size) |
1745
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
494 if flagUpdates: |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
495 prog.carryFlowDst = tmpvar |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
496 prog.lastA = params[1] |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
497 prog.lastB = params[0] |
a8f04b0ab744
Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1744
diff
changeset
|
498 prog.lastBFlow = params[0] |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
499 scope = prog.getRootScope() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
500 if not scope.resolveLocal(tmpvar): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
501 scope.addLocal(tmpvar, size) |
1719
fb5ae8c20b85
Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1716
diff
changeset
|
502 prog.lastDst = rawParams[1] |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
503 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
504 |
1723
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
505 def _asrCImpl(prog, params, rawParams, flagUpdates): |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
506 needsCarry = False |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
507 if flagUpdates: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
508 for flag in flagUpdates: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
509 calc = prog.flags.flagCalc[flag] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
510 if calc == 'carry': |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
511 needsCarry = True |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
512 decl = '' |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
513 size = prog.paramSize(rawParams[2]) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
514 if needsCarry: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
515 decl,name = prog.getTemp(size * 2) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
516 dst = prog.carryFlowDst = name |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
517 prog.lastA = params[0] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
518 else: |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
519 dst = params[2] |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
520 mask = 1 << (size - 1) |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
521 return decl + '\n\t{dst} = ({a} >> {b}) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format( |
b757ebc59851
Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1722
diff
changeset
|
522 a = params[0], b = params[1], dst = dst, mask = mask, size=size) |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
523 |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
524 def _sext(size, src): |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
525 if size == 16: |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
526 return src | 0xFF00 if src & 0x80 else src |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
527 else: |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
528 return src | 0xFFFF0000 if src & 0x8000 else src |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
529 |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
530 def _sextCImpl(prog, params, rawParms): |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
531 if params[0] == 16: |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
532 fmt = '\n\t{dst} = {src} & 0x80 ? {src} | 0xFF00 : {src};' |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
533 else: |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
534 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src};' |
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
535 return fmt.format(src=params[1], dst=params[2]) |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
536 |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
537 def _getCarryCheck(prog): |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
538 carryFlag = None |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
539 for flag in prog.flags.flagCalc: |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
540 if prog.flags.flagCalc[flag] == 'carry': |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
541 carryFlag = flag |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
542 if carryFlag is None: |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
543 raise Exception('adc requires a defined carry flag') |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
544 carryStorage = prog.flags.getStorage(carryFlag) |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
545 if type(carryStorage) is tuple: |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
546 reg,bit = carryStorage |
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
547 reg = prog.resolveReg(reg, None, (), False) |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
548 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit) |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
549 else: |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
550 return prog.resolveReg(carryStorage, None, (), False) |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
551 |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
552 def _adcCImpl(prog, params, rawParams, flagUpdates): |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
553 needsCarry = needsOflow = needsHalf = False |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
554 if flagUpdates: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
555 for flag in flagUpdates: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
556 calc = prog.flags.flagCalc[flag] |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
557 if calc == 'carry': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
558 needsCarry = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
559 elif calc == 'half-carry': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
560 needsHalf = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
561 elif calc == 'overflow': |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
562 needsOflow = True |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
563 decl = '' |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
564 carryCheck = _getCarryCheck(prog) |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
565 if needsCarry or needsOflow or needsHalf: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
566 size = prog.paramSize(rawParams[2]) |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
567 if needsCarry: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
568 size *= 2 |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
569 decl,name = prog.getTemp(size) |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
570 dst = prog.carryFlowDst = name |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
571 prog.lastA = params[0] |
1744
91aa789e57bd
Fixed half-carry flag calcuation for adc/sbc in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1742
diff
changeset
|
572 prog.lastB = params[1] |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
573 prog.lastBFlow = '(~{b})'.format(b=params[1]) |
1709
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
574 else: |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
575 dst = params[2] |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
576 return decl + '\n\t{dst} = {a} + {b} + ({check} ? 1 : 0);'.format(dst = dst, |
9c058ea77b7a
Implementation of carry/overflow flags for adc instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1708
diff
changeset
|
577 a = params[0], b = params[1], check = carryCheck |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
578 ) |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
579 |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
580 def _sbcCImpl(prog, params, rawParams, flagUpdates): |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
581 needsCarry = needsOflow = needsHalf = False |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
582 if flagUpdates: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
583 for flag in flagUpdates: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
584 calc = prog.flags.flagCalc[flag] |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
585 if calc == 'carry': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
586 needsCarry = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
587 elif calc == 'half-carry': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
588 needsHalf = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
589 elif calc == 'overflow': |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
590 needsOflow = True |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
591 decl = '' |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
592 carryCheck = _getCarryCheck(prog) |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
593 if needsCarry or needsOflow or needsHalf: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
594 size = prog.paramSize(rawParams[2]) |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
595 if needsCarry: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
596 size *= 2 |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
597 decl,name = prog.getTemp(size) |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
598 dst = prog.carryFlowDst = name |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
599 prog.lastA = params[1] |
1744
91aa789e57bd
Fixed half-carry flag calcuation for adc/sbc in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1742
diff
changeset
|
600 prog.lastB = params[0] |
1711
87d4f0b4bf1d
Actually correct overflow flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1710
diff
changeset
|
601 prog.lastBFlow = params[0] |
1710
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
602 else: |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
603 dst = params[2] |
2344b3650b38
Fix sbc and implement carry/overflow flags for it in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1709
diff
changeset
|
604 return decl + '\n\t{dst} = {b} - {a} - ({check} ? 1 : 0);'.format(dst = dst, |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
605 a = params[0], b = params[1], check=_getCarryCheck(prog) |
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
606 ) |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
607 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
608 def _rolCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
609 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
610 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
611 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
612 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
613 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
614 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
615 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
616 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
617 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
618 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
619 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
620 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
621 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
622 return decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} - {b});'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
623 a = params[0], b = params[1], size=size |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
624 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
625 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
626 def _rlcCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
627 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
628 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
629 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
630 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
631 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
632 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
633 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
634 carryCheck = _getCarryCheck(prog) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
635 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
636 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
637 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
638 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
639 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
640 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
641 return decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} + 1 - {b}) | ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
642 a = params[0], b = params[1], size=size, check=carryCheck |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
643 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
644 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
645 def _rorCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
646 size = prog.paramSize(rawParams[2]) |
1722
ac809d044cab
Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1721
diff
changeset
|
647 return '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = params[2], |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
648 a = params[0], b = params[1], size=size |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
649 ) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
650 |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
651 def _rrcCImpl(prog, params, rawParams, flagUpdates): |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
652 needsCarry = False |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
653 if flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
654 for flag in flagUpdates: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
655 calc = prog.flags.flagCalc[flag] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
656 if calc == 'carry': |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
657 needsCarry = True |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
658 decl = '' |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
659 carryCheck = _getCarryCheck(prog) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
660 size = prog.paramSize(rawParams[2]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
661 if needsCarry: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
662 decl,name = prog.getTemp(size * 2) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
663 dst = prog.carryFlowDst = name |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
664 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
665 dst = params[2] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
666 return decl + '\n\t{dst} = {a} >> {b} | {a} << ({size} + 1 - {b}) | ({check} ? 1 : 0) << ({size}-{b});'.format(dst = dst, |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
667 a = params[0], b = params[1], size=size, check=carryCheck |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
668 ) |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
669 |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
670 def _updateSyncCImpl(prog, params): |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
671 return '\n\tsync_cycle = {sync}(context, target_cycle);'.format(sync=prog.sync_cycle) |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
672 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
673 _opMap = { |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
674 'mov': Op(lambda val: val).cUnaryOperator(''), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
675 'not': Op(lambda val: ~val).cUnaryOperator('~'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
676 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
677 'neg': Op(lambda val: -val).cUnaryOperator('-'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
678 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), |
1701
4fd34fde390c
Added adc instruction to CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1700
diff
changeset
|
679 'adc': Op().addImplementation('c', 2, _adcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
680 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), |
1702
73ac2e59fa3f
Implemented sbc instruction in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1701
diff
changeset
|
681 'sbc': Op().addImplementation('c', 2, _sbcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
682 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
683 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
684 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
685 'rol': Op().addImplementation('c', 2, _rolCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
686 'rlc': Op().addImplementation('c', 2, _rlcCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
687 'ror': Op().addImplementation('c', 2, _rorCImpl), |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
688 'rrc': Op().addImplementation('c', 2, _rrcCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
689 'and': Op(lambda a, b: a & b).cBinaryOperator('&'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
690 'or': Op(lambda a, b: a | b).cBinaryOperator('|'), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
691 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'), |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
692 'abs': Op(lambda val: abs(val)).addImplementation( |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
693 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
694 ), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
695 'cmp': Op().addImplementation('c', None, _cmpCImpl), |
1697
44d8c6e61ad4
Added new sext instruction for sign extension to CPU sdl
Michael Pavone <pavone@retrodev.com>
parents:
1621
diff
changeset
|
696 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
697 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
698 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) |
1753
33ec5df77fac
Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents:
1752
diff
changeset
|
699 ) + _updateSyncCImpl(prog, params)), |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 'cycles': Op().addImplementation('c', None, |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
701 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
702 params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
703 ) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 ), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 'addsize': Op( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
706 lambda a, b: b + (2 * a if a else 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
707 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + {sz} ? {sz} * 2 : 1;'.format( |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
708 dst = params[2], sz = params[0], val = params[1] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
709 )), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
710 'decsize': Op( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
711 lambda a, b: b - (2 * a if a else 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
712 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - {sz} ? {sz} * 2 : 1;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
713 dst = params[2], sz = params[0], val = params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 )), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
715 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl), |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
716 'dispatch': Op().addImplementation('c', None, _dispatchCImpl), |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
717 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl), |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
718 'update_sync': Op().addImplementation('c', None, _updateSyncCImpl) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 } |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
720 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
721 #represents a simple DSL instruction |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
722 class NormalOp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
723 def __init__(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
724 self.op = parts[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
725 self.params = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
726 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
727 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
728 procParams = [] |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
729 allParamsConst = flagUpdates is None and not prog.conditional |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
730 opDef = _opMap.get(self.op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
731 for param in self.params: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
732 allowConst = (self.op in prog.subroutines or len(procParams) != len(self.params) - 1) and param in parent.regValues |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
733 isDst = (not opDef is None) and len(procParams) in opDef.outOp |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 if (not type(param) is int) and len(procParams) != len(self.params) - 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 allParamsConst = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 procParams.append(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 if self.op == 'meta': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 param,_,index = self.params[1].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 if index: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 index = (parent.resolveLocal(index) or index) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 if index in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 index = str(fieldVals[index]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 param = param + '.' + index |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 param = parent.resolveLocal(param) or param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 if param in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 param = fieldVals[index] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 prog.meta[self.params[0]] = param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
752 elif self.op == 'dis': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 #TODO: Disassembler |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
755 elif not opDef is None: |
1716
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
756 if opDef.numParams() > len(procParams): |
04cafe626118
Better error reporting when an instruction is given an insufficient number of parameters
Michael Pavone <pavone@retrodev.com>
parents:
1715
diff
changeset
|
757 raise Exception('Insufficient params for ' + self.op + ' (' + ', '.join(self.params) + ')') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 if opDef.canEval() and allParamsConst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 #do constant folding |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 if opDef.numArgs() >= len(procParams): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 dst = self.params[opDef.numArgs()] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 result = opDef.evaluate(procParams[:opDef.numArgs()]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 while dst in prog.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 dst = prog.meta[dst] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 maybeLocal = parent.resolveLocal(dst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 if maybeLocal: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 dst = maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 parent.regValues[dst] = result |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 if prog.isReg(dst): |
1699
93103ad9d7f7
Fix constant propagation to a non-ephemeral destination in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1698
diff
changeset
|
771 shortProc = (procParams[0], procParams[-1]) |
93103ad9d7f7
Fix constant propagation to a non-ephemeral destination in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1698
diff
changeset
|
772 shortParams = (self.params[0], self.params[-1]) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
773 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
774 else: |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
775 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates)) |
1728
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
776 for dstIdx in opDef.outOp: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
777 dst = self.params[dstIdx] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
778 while dst in prog.meta: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
779 dst = prog.meta[dst] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
780 if dst in parent.regValues: |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
781 del parent.regValues[dst] |
b0e01e64d76d
Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1725
diff
changeset
|
782 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
783 elif self.op in prog.subroutines: |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
784 procParams = [] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
785 for param in self.params: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
786 begin,sep,end = param.partition('.') |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
787 if sep: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
788 if end in fieldVals: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
789 param = begin + '.' + str(fieldVals[end]) |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
790 else: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
791 if param in fieldVals: |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
792 param = fieldVals[param] |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
793 procParams.append(param) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 prog.lastOp = self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
799 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 return '\n\t' + self.op + ' ' + ' '.join(self.params) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 #represents a DSL switch construct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 class Switch(ChildBlock): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 def __init__(self, parent, param): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 self.op = 'switch' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 self.parent = parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 self.param = param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 self.cases = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 self.regValues = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
810 self.current_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 self.case_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 self.current_case = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
813 self.default = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 self.default_locals = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 if op.op == 'case': |
1619
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
818 val = int(op.params[0], 16) if op.params[0].startswith('0x') else int(op.params[0]) |
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
819 self.cases[val] = self.current_case = [] |
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
820 self.case_locals[val] = self.current_locals = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 elif op.op == 'default': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 self.default = self.current_case = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 self.default_locals = self.current_locals = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 elif self.current_case == None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 raise ion('Orphan instruction in switch') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 elif op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 name = op.params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 size = op.params[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 self.current_locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 self.current_case.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 def resolveLocal(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 if name in self.current_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 return name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 return self.parent.resolveLocal(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 def addLocal(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 self.current_locals[name] = size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 def localSize(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 if name in self.current_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 return self.current_locals[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 return self.parent.localSize(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
846 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
847 prog.pushScope(self) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 param = prog.resolveParam(self.param, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 if type(param) is int: |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
850 self.regValues = self.parent.regValues |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
851 if param in self.cases: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
852 self.current_locals = self.case_locals[param] |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
853 output.append('\n\t{') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
854 for local in self.case_locals[param]: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
855 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
856 self.processOps(prog, fieldVals, output, otype, self.cases[param]) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
857 output.append('\n\t}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
858 elif self.default: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
859 self.current_locals = self.default_locals |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
860 output.append('\n\t{') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
861 for local in self.default_locals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
862 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
863 self.processOps(prog, fieldVals, output, otype, self.default) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
864 output.append('\n\t}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 else: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
866 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
867 prog.conditional = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 output.append('\n\tswitch(' + param + ')') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 output.append('\n\t{') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 for case in self.cases: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
871 temp = prog.temp.copy() |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
872 self.current_locals = self.case_locals[case] |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
873 self.regValues = dict(self.parent.regValues) |
1619
0e8438a4c76f
Clean up warnings from -1 case
Michael Pavone <pavone@retrodev.com>
parents:
1618
diff
changeset
|
874 output.append('\n\tcase {0}U: '.format(case) + '{') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 for local in self.case_locals[case]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
877 self.processOps(prog, fieldVals, output, otype, self.cases[case]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 output.append('\n\tbreak;') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
880 prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 if self.default: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
882 temp = prog.temp.copy() |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
883 self.current_locals = self.default_locals |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
884 self.regValues = dict(self.parent.regValues) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 output.append('\n\tdefault: {') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 for local in self.default_locals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local)) |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
888 self.processOps(prog, fieldVals, output, otype, self.default) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
889 prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
891 prog.conditional = oldCond |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
892 prog.popScope() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 keys = self.cases.keys() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 keys.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 lines = ['\n\tswitch'] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 for case in keys: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 lines.append('\n\tcase {0}'.format(case)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 lines.append(''.join([str(op) for op in self.cases[case]])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 return ''.join(lines) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 def _geuCImpl(prog, parent, fieldVals, output): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 if prog.lastOp.op == 'cmp': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 output.pop() |
1616
8c78543c4783
Fix implementation cmp+condition version of if in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1615
diff
changeset
|
908 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
8c78543c4783
Fix implementation cmp+condition version of if in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1615
diff
changeset
|
909 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{' |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 else: |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
911 raise Exception(">=U not implemented in the general case yet") |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
912 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
913 def _eqCImpl(prog, parent, fieldVals, output): |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
914 return '\n\tif (!{a}) {'.format(a=prog.resolveParam(prog.lastDst, None, {})) |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
915 |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
916 def _neqCImpl(prog, parent, fieldVals, output): |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
917 return '\n\tif ({a}) {'.format(a=prog.resolveParam(prog.lastDst, None, {})) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 _ifCmpImpl = { |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 'c': { |
1733
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
921 '>=U': _geuCImpl, |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
922 '=': _eqCImpl, |
1f0a86f5e055
Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1728
diff
changeset
|
923 '!=': _neqCImpl |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 } |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 } |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 #represents a DSL conditional construct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 class If(ChildBlock): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 def __init__(self, parent, cond): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 self.op = 'if' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 self.parent = parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 self.cond = cond |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 self.body = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 self.elseBody = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 self.curBody = self.body |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 self.locals = {} |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
936 self.elseLocals = {} |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
937 self.curLocals = self.locals |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
938 self.regValues = None |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 def addOp(self, op): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 if op.op in ('case', 'arg'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 raise Exception(self.op + ' is not allows inside an if block') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 if op.op == 'local': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 name = op.params[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 size = op.params[1] |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
946 self.curLocals[name] = size |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 elif op.op == 'else': |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
948 self.curLocals = self.elseLocals |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 self.curBody = self.elseBody |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 self.curBody.append(op) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
953 def localSize(self, name): |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
954 return self.curLocals.get(name) |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
955 |
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
956 def resolveLocal(self, name): |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
957 if name in self.curLocals: |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
958 return name |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
959 return self.parent.resolveLocal(name) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
960 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
961 def _genTrueBody(self, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
962 self.curLocals = self.locals |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
963 subOut = [] |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
964 self.processOps(prog, fieldVals, subOut, otype, self.body) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
965 for local in self.locals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
966 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local)) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
967 output += subOut |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
968 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
969 def _genFalseBody(self, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
970 self.curLocals = self.elseLocals |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
971 subOut = [] |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
972 self.processOps(prog, fieldVals, subOut, otype, self.elseBody) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
973 for local in self.elseLocals: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
974 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local)) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
975 output += subOut |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
976 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
977 def _genConstParam(self, param, prog, fieldVals, output, otype): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
978 if param: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
979 self._genTrueBody(prog, fieldVals, output, otype) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
980 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
981 self._genFalseBody(prog, fieldVals, output, otype) |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
982 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
983 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
984 self.regValues = parent.regValues |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 try: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
986 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 except Exception: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 if self.cond in _ifCmpImpl[otype]: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
989 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
990 prog.conditional = True |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
991 temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
993 self._genTrueBody(prog, fieldVals, output, otype) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
994 prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 if self.elseBody: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
996 temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 output.append('\n\t} else {') |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
998 self._genFalseBody(prog, fieldVals, output, otype) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
999 prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1001 prog.conditional = oldCond |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 cond = prog.resolveParam(self.cond, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 if type(cond) is int: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1005 self._genConstParam(cond, prog, fieldVals, output, otype) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 else: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1007 temp = prog.temp.copy() |
1614
c9639139aedf
Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents:
1613
diff
changeset
|
1008 output.append('\n\tif ({cond}) '.format(cond=cond) + '{') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1009 oldCond = prog.conditional |
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1010 prog.conditional = True |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1011 self._genTrueBody(prog, fieldVals, output, otype) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1012 prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 if self.elseBody: |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1014 temp = prog.temp.copy() |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 output.append('\n\t} else {') |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1016 self._genFalseBody(prog, fieldVals, output, otype) |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1017 prog.temp = temp |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 output.append('\n\t}') |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1019 prog.conditional = oldCond |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 lines = ['\n\tif'] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 for op in self.body: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1025 lines.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 return ''.join(lines) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 class Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 self.regs = {} |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1032 self.pointers = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 self.regArrays = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 self.regToArray = {} |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1035 self.addReg('cycles', 32) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 def addReg(self, name, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 self.regs[name] = size |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1039 |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1040 def addPointer(self, name, size, count): |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1041 self.pointers[name] = (size, count) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 def addRegArray(self, name, size, regs): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 self.regArrays[name] = (size, regs) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 idx = 0 |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1046 if not type(regs) is int: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1047 for reg in regs: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1048 self.regs[reg] = size |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1049 self.regToArray[reg] = (name, idx) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1050 idx += 1 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 return name in self.regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 def isRegArray(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 return name in self.regArrays |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 def isRegArrayMember(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 return name in self.regToArray |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 def arrayMemberParent(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 return self.regToArray[name][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 def arrayMemberIndex(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 return self.regToArray[name][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 def arrayMemberName(self, array, index): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1068 if type(index) is int and not type(self.regArrays[array][1]) is int: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 return self.regArrays[array][1][index] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 return None |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1072 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1073 def isNamedArray(self, array): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1074 return array in self.regArrays and type(self.regArrays[array][1]) is int |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1075 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1076 def processLine(self, parts): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1077 if len(parts) == 3: |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1078 if parts[1].startswith('ptr'): |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1079 self.addPointer(parts[0], parts[1][3:], int(parts[2])) |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1080 else: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1081 self.addRegArray(parts[0], int(parts[1]), int(parts[2])) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1082 elif len(parts) > 2: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1083 self.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1084 else: |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1085 if parts[1].startswith('ptr'): |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1086 self.addPointer(parts[0], parts[1][3:], 1) |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1087 else: |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1088 self.addReg(parts[0], int(parts[1])) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1089 return self |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1090 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1091 def writeHeader(self, otype, hFile): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1092 fieldList = [] |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
1093 for pointer in self.pointers: |
1735
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1094 stars = '*' |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1095 ptype, count = self.pointers[pointer] |
1735
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1096 while ptype.startswith('ptr'): |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1097 stars += '*' |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1098 ptype = ptype[3:] |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1099 if ptype.isdigit(): |
ca2336469397
Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents:
1734
diff
changeset
|
1100 ptype = 'uint{sz}_t'.format(sz=ptype) |
1750
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1101 if count > 1: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1102 arr = '[{n}]'.format(n=count) |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1103 else: |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1104 arr = '' |
01236179fc71
Optimization to memory access in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1749
diff
changeset
|
1105 hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1106 for reg in self.regs: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1107 if not self.isRegArrayMember(reg): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1108 fieldList.append((self.regs[reg], 1, reg)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1109 for arr in self.regArrays: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1110 size,regs = self.regArrays[arr] |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1111 if not type(regs) is int: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1112 regs = len(regs) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1113 fieldList.append((size, regs, arr)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1114 fieldList.sort() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1115 fieldList.reverse() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1116 for size, count, name in fieldList: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1117 if count > 1: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1118 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1119 else: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1120 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1121 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1122 class Flags: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1123 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1124 self.flagBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1125 self.flagCalc = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1126 self.flagStorage = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1127 self.flagReg = None |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1128 self.storageToFlags = {} |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1129 self.maxBit = -1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1130 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1131 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1132 if parts[0] == 'register': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1133 self.flagReg = parts[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1134 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1135 flag,bit,calc,storage = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1136 bit,_,top = bit.partition('-') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1137 bit = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1138 if top: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 top = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1140 if top > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1141 self.maxBit = top |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1142 self.flagBits[flag] = (bit,top) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1144 if bit > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 self.maxBit = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1146 self.flagBits[flag] = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1147 self.flagCalc[flag] = calc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 self.flagStorage[flag] = storage |
1747
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1149 storage,_,storebit = storage.partition('.') |
89ddf41a50bb
Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1745
diff
changeset
|
1150 self.storageToFlags.setdefault(storage, []).append((storebit, flag)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1151 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1152 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1153 def getStorage(self, flag): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1154 if not flag in self.flagStorage: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1155 raise Exception('Undefined flag ' + flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1156 loc,_,bit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1157 if bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1158 return (loc, int(bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1159 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1160 return loc |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1161 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1162 def parseFlagUpdate(self, flagString): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1163 last = '' |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1164 autoUpdate = set() |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1165 explicit = {} |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1166 for c in flagString: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1167 if c.isdigit(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1168 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1169 num = int(c) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1170 if num > 1: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1171 raise Exception(c + ' is not a valid digit for update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1172 explicit[last] = num |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1173 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1174 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1175 raise Exception('Digit must follow flag letter in update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1176 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1177 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1178 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1179 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1180 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1181 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1182 return (autoUpdate, explicit) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1183 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1184 def disperseFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1185 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1186 src = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1187 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1188 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1189 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1190 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1191 bot,top = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1192 mask = ((1 << (top + 1 - bot)) - 1) << bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1193 output.append('\n\t{dst} = {src} & mask;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1194 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1195 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1196 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1197 bitToFlag[self.flagBits[flag]] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1198 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1199 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1200 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1201 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1202 field,_,dstbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1203 dst = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1204 if dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1205 dstbit = int(dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1206 multi.setdefault(dst, []).append((dstbit, bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1207 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1208 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1209 for dst in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1210 didClear = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1211 direct = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1212 for dstbit, bit in multi[dst]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1213 if dstbit == bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1214 direct.append(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1215 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1216 if not didClear: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1217 output.append('\n\t{dst} = 0;'.format(dst=dst)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1218 didClear = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1219 if dstbit > bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1220 shift = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1221 diff = dstbit - bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1222 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1223 shift = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1224 diff = bit - dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1225 output.append('\n\t{dst} |= {src} {shift} {diff} & {mask};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1226 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1227 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1228 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1229 if len(direct) == len(multi[dst]): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1230 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1231 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1232 mask = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1233 for bit in direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1234 mask = mask | (1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1235 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1236 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1237 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1238 def coalesceFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1239 dst = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1240 output = ['\n\t{dst} = 0;'.format(dst=dst)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1241 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1242 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1243 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1244 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1245 bot,_ = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1246 src = prog.resolveReg(self.flagStorage[flag], None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1247 if bot: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1248 output.append('\n\t{dst} |= {src} << {shift};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1249 dst=dst, src = src, shift = bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1250 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1251 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1252 output.append('\n\t{dst} |= {src};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1253 dst=dst, src = src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1254 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1255 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1256 bitToFlag[bit] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1257 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1258 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1259 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1260 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1261 field,_,srcbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1262 src = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1263 if srcbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1264 srcbit = int(srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1265 multi.setdefault(src, []).append((srcbit,bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1266 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1267 output.append('\n\tif ({src}) {{\n\t\t{dst} |= 1 << {bit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1268 dst=dst, src=src, bit=bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1269 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1270 for src in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1271 direct = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1272 for srcbit, dstbit in multi[src]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1273 if srcbit == dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1274 direct = direct | (1 << srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1275 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1276 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} |= 1 << {dstbit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1277 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1278 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1279 if direct: |
1698
90272218469c
Fixed missing semicolon in coalesceFlags
Michael Pavone <pavone@retrodev.com>
parents:
1697
diff
changeset
|
1280 output.append('\n\t{dst} |= {src} & {mask};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1281 dst=dst, src=src, mask=direct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1282 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1283 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1284 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1285 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1286 class Program: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1287 def __init__(self, regs, instructions, subs, info, flags): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1288 self.regs = regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1289 self.instructions = instructions |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1290 self.subroutines = subs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1291 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1292 self.booleans = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1293 self.prefix = info.get('prefix', [''])[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1294 self.opsize = int(info.get('opcode_size', ['8'])[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1295 self.extra_tables = info.get('extra_tables', []) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1296 self.context_type = self.prefix + 'context' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1297 self.body = info.get('body', [None])[0] |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1298 self.interrupt = info.get('interrupt', [None])[0] |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1299 self.sync_cycle = info.get('sync_cycle', [None])[0] |
1620
a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents:
1619
diff
changeset
|
1300 self.includes = info.get('include', []) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1301 self.flags = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1302 self.lastDst = None |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1303 self.scopes = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1304 self.currentScope = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1305 self.lastOp = None |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1306 self.carryFlowDst = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1307 self.lastA = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
1308 self.lastB = None |
1708
5bfed2eedc9d
Fixed flag calculation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1707
diff
changeset
|
1309 self.lastBFlow = None |
1737
2207cd2bae14
Fixed some issues involving conditional execution and temporaries/constant folding
Michael Pavone <pavone@retrodev.com>
parents:
1735
diff
changeset
|
1310 self.conditional = False |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1311 self.declares = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1312 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1313 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1314 pieces = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1315 for reg in self.regs: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1316 pieces.append(str(self.regs[reg])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1317 for name in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1318 pieces.append('\n'+str(self.subroutines[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1319 for instruction in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1320 pieces.append('\n'+str(instruction)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1321 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1322 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1323 def writeHeader(self, otype, header): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1324 hFile = open(header, 'w') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1325 macro = header.upper().replace('.', '_') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1326 hFile.write('#ifndef {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1327 hFile.write('\n#define {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1328 hFile.write('\n#include "backend.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1329 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1330 hFile.write('\n\tcpu_options gen;') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1331 hFile.write('\n}} {0}options;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1332 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1333 hFile.write('\n\t{0}options *opts;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1334 self.regs.writeHeader(otype, hFile) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1335 hFile.write('\n}} {0}context;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1336 hFile.write('\n') |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
1337 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type)) |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1338 for decl in self.declares: |
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1339 hFile.write('\n' + decl) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1340 hFile.write('\n#endif //{0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1341 hFile.write('\n') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1342 hFile.close() |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1343 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1344 def _buildTable(self, otype, table, body, lateBody): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1345 pieces = [] |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1346 opmap = [None] * (1 << self.opsize) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1347 bodymap = {} |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1348 if table in self.instructions: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1349 instructions = self.instructions[table] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1350 instructions.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1351 for inst in instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1352 for val in inst.allValues(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1353 if opmap[val] is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1354 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1355 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1356 self.needFlagCoalesce = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1357 self.needFlagDisperse = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1358 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1359 opmap[val] = inst.generateName(val) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1360 bodymap[val] = inst.generateBody(val, self, otype) |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1361 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1362 if self.dispatch == 'call': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1363 pieces.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1364 for inst in range(0, len(opmap)): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1365 op = opmap[inst] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1366 if op is None: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1367 pieces.append('\n\tunimplemented,') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1368 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1369 pieces.append('\n\t' + op + ',') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1370 body.append(bodymap[inst]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1371 pieces.append('\n};') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1372 elif self.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1373 body.append('\n\tstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1374 for inst in range(0, len(opmap)): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1375 op = opmap[inst] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1376 if op is None: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1377 body.append('\n\t\t&&unimplemented,') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1378 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1379 body.append('\n\t\t&&' + op + ',') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1380 lateBody.append(bodymap[inst]) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1381 body.append('\n\t};') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1382 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1383 raise Exception("unimplmeneted dispatch type " + self.dispatch) |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1384 body.extend(pieces) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1385 |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1386 def nextInstruction(self, otype): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1387 output = [] |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1388 if self.dispatch == 'goto': |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1389 if self.interrupt in self.subroutines: |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1390 output.append('\n\tif (context->cycles >= sync_cycle) {') |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1391 output.append('\n\tif (context->cycles >= target_cycle) { return; }') |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1392 if self.interrupt in self.subroutines: |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1393 self.meta = {} |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1394 self.temp = {} |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1395 self.subroutines[self.interrupt].inline(self, [], output, otype, None) |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1396 output.append('\n\t}') |
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1397 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1398 self.meta = {} |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1399 self.temp = {} |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1400 self.subroutines[self.body].inline(self, [], output, otype, None) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1401 return output |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1402 |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1403 def build(self, otype): |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1404 body = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1405 pieces = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1406 for include in self.includes: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1407 body.append('#include "{0}"\n'.format(include)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1408 if self.dispatch == 'call': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1409 body.append('\nstatic void unimplemented({pre}context *context)'.format(pre = self.prefix)) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1410 body.append('\n{') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1411 body.append('\n\tfatal_error("Unimplemented instruction\\n");') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1412 body.append('\n}\n') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1413 body.append('\ntypedef void (*impl_fun)({pre}context *context);'.format(pre=self.prefix)) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1414 for table in self.extra_tables: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1415 body.append('\nstatic impl_fun impl_{name}[{sz}];'.format(name = table, sz=(1 << self.opsize))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1416 body.append('\nstatic impl_fun impl_main[{sz}];'.format(sz=(1 << self.opsize))) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1417 elif self.dispatch == 'goto': |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1418 body.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1419 body.append('\n{') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1420 |
1740
28ab56ff8cea
Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents:
1737
diff
changeset
|
1421 for table in self.extra_tables: |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1422 self._buildTable(otype, table, body, pieces) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1423 self._buildTable(otype, 'main', body, pieces) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1424 if self.dispatch == 'call' and self.body in self.subroutines: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1425 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1426 pieces.append('\n{') |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1427 pieces.append('\n\tuint32_t sync_cycle = {sync}(context, target_cycle);'.format(sync=self.sync_cycle)) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1428 pieces.append('\n\twhile (context->cycles < target_cycle)') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1429 pieces.append('\n\t{') |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1430 #TODO: Handle interrupts in call dispatch mode |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1431 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1432 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1433 self.subroutines[self.body].inline(self, [], pieces, otype, None) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1434 pieces.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1435 pieces.append('\n}') |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1436 elif self.dispatch == 'goto': |
1752
d6d4c006a7b3
Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents:
1750
diff
changeset
|
1437 body.append('\n\tuint32_t sync_cycle = {sync}(context, target_cycle);'.format(sync=self.sync_cycle)) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1438 body += self.nextInstruction(otype) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1439 pieces.append('\nunimplemented:') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1440 pieces.append('\n\tfatal_error("Unimplemented instruction\\n");') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1441 pieces.append('\n}') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1442 return ''.join(body) + ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1443 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1444 def checkBool(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1445 if not name in self.booleans: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1446 raise Exception(name + ' is not a defined boolean flag') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1447 return self.booleans[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1448 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1449 def getTemp(self, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1450 if size in self.temp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1451 return ('', self.temp[size]) |
1742
6290c88949bd
Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1740
diff
changeset
|
1452 self.temp[size] = 'gen_tmp{sz}__'.format(sz=size); |
6290c88949bd
Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1740
diff
changeset
|
1453 return ('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size), self.temp[size]) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1454 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1455 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1456 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1457 while keepGoing: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1458 keepGoing = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1459 try: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1460 if type(param) is int: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1461 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1462 elif param.startswith('0x'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1463 param = int(param, 16) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1464 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1465 param = int(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1466 except ValueError: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1467 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1468 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1469 if param in parent.regValues and allowConstant: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1470 return parent.regValues[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1471 maybeLocal = parent.resolveLocal(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1472 if maybeLocal: |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1473 if isdst: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1474 self.lastDst = param |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1475 return maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1476 if param in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1477 param = fieldVals[param] |
1721
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1478 fieldVals = {} |
0e5df2bc0f9f
Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
1719
diff
changeset
|
1479 keepGoing = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1480 elif param in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1481 param = self.meta[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1482 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1483 elif self.isReg(param): |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1484 return self.resolveReg(param, parent, fieldVals, isdst) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1485 if isdst: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1486 self.lastDst = param |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1487 return param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1488 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1489 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1490 if not type(name) is str: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1491 return False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1492 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1493 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1494 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1495 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1496 return self.regs.isRegArray(begin) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1497 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1498 return self.regs.isReg(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1499 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1500 def resolveReg(self, name, parent, fieldVals, isDst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1501 begin,sep,end = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1502 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1503 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1504 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1505 if not self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1506 end = self.resolveParam(end, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1507 if not type(end) is int and self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1508 arrayName = self.regs.arrayMemberParent(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1509 end = self.regs.arrayMemberIndex(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1510 if arrayName != begin: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1511 end = 'context->{0}[{1}]'.format(arrayName, end) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1512 if self.regs.isNamedArray(begin): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1513 regName = self.regs.arrayMemberName(begin, end) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1514 else: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1515 regName = '{0}.{1}'.format(begin, end) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1516 ret = 'context->{0}[{1}]'.format(begin, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1517 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1518 regName = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1519 if self.regs.isRegArrayMember(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1520 arr,idx = self.regs.regToArray[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1521 ret = 'context->{0}[{1}]'.format(arr, idx) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1522 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1523 ret = 'context->' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1524 if regName == self.flags.flagReg: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1525 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1526 self.needFlagDisperse = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1527 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1528 self.needFlagCoalesce = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1529 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1530 self.lastDst = regName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1531 return ret |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1532 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1533 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1534 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1535 def paramSize(self, name): |
1715
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1536 if name in self.meta: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1537 return self.paramSize(self.meta[name]) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1538 for i in range(len(self.scopes) -1, -1, -1): |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1539 size = self.scopes[i].localSize(name) |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1540 if size: |
4fd84c3efc72
Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents:
1713
diff
changeset
|
1541 return size |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1542 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1543 if sep and self.regs.isRegArray(begin): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1544 return self.regs.regArrays[begin][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1545 if self.regs.isReg(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1546 return self.regs.regs[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1547 return 32 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1548 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1549 def pushScope(self, scope): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1550 self.scopes.append(scope) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1551 self.currentScope = scope |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1552 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1553 def popScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1554 ret = self.scopes.pop() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1555 self.currentScope = self.scopes[-1] if self.scopes else None |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1556 return ret |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1557 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1558 def getRootScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1559 return self.scopes[0] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1560 |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1561 def parse(args): |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1562 f = args.source |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1563 instructions = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1564 subroutines = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1565 registers = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1566 flags = None |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1567 declares = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1568 errors = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1569 info = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1570 line_num = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1571 cur_object = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1572 for line in f: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1573 line_num += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1574 line,_,comment = line.partition('#') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1575 if not line.strip(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1576 continue |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1577 if line[0].isspace(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1578 if not cur_object is None: |
1754
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1579 sep = True |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1580 parts = [] |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1581 while sep: |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1582 before,sep,after = line.partition('"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1583 before = before.strip() |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1584 if before: |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1585 parts += [el.strip() for el in before.split(' ')] |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1586 if sep: |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1587 #TODO: deal with escaped quotes |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1588 inside,sep,after = after.partition('"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1589 parts.append('"' + inside + '"') |
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1590 line = after |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1591 if type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1592 cur_object[parts[0]] = parts[1:] |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1593 elif type(cur_object) is list: |
1754
043cf458704c
Basic support for string operands in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1753
diff
changeset
|
1594 cur_object.append(' '.join(parts)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1595 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1596 cur_object = cur_object.processLine(parts) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1597 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1598 # if type(cur_object) is Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1599 # if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1600 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1601 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1602 # cur_object.addReg(parts[0], int(parts[1])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1603 # elif type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1604 # cur_object[parts[0]] = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1605 # elif parts[0] == 'switch': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1606 # o = Switch(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1607 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1608 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1609 # elif parts[0] == 'if': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1610 # o = If(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1611 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1612 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1613 # elif parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1614 # cur_object = cur_object.parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1615 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1616 # cur_object.addOp(NormalOp(parts)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1617 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1618 errors.append("Orphan instruction on line {0}".format(line_num)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1619 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1620 parts = line.split(' ') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1621 if len(parts) > 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1622 if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1623 table,bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1624 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1625 bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1626 table = 'main' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1627 value = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1628 fields = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1629 curbit = len(bitpattern) - 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1630 for char in bitpattern: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1631 value <<= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1632 if char in ('0', '1'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1633 value |= int(char) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1634 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1635 if char in fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1636 fields[char] = (curbit, fields[char][1] + 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1637 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1638 fields[char] = (curbit, 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1639 curbit -= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1640 cur_object = Instruction(value, fields, name.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1641 instructions.setdefault(table, []).append(cur_object) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1642 elif line.strip() == 'regs': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1643 if registers is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1644 registers = Registers() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1645 cur_object = registers |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1646 elif line.strip() == 'info': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1647 cur_object = info |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1648 elif line.strip() == 'flags': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1649 if flags is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1650 flags = Flags() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1651 cur_object = flags |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1652 elif line.strip() == 'declare': |
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1653 cur_object = declares |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1654 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1655 cur_object = SubRoutine(line.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1656 subroutines[cur_object.name] = cur_object |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1657 if errors: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1658 print(errors) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1659 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1660 p = Program(registers, instructions, subroutines, info, flags) |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1661 p.dispatch = args.dispatch |
1748
48a43dff4dc0
Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents:
1747
diff
changeset
|
1662 p.declares = declares |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1663 p.booleans['dynarec'] = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1664 p.booleans['interp'] = True |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1665 if args.define: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1666 for define in args.define: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1667 name,sep,val = define.partition('=') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1668 name = name.strip() |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1669 val = val.strip() |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1670 if sep: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1671 p.booleans[name] = bool(val) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1672 else: |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1673 p.booleans[name] = True |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1674 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1675 if 'header' in info: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1676 print('#include "{0}"'.format(info['header'][0])) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1677 p.writeHeader('c', info['header'][0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1678 print('#include "util.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1679 print('#include <stdlib.h>') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1680 print(p.build('c')) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1681 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1682 def main(argv): |
1749
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1683 from argparse import ArgumentParser, FileType |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1684 argParser = ArgumentParser(description='CPU emulator DSL compiler') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1685 argParser.add_argument('source', type=FileType('r')) |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1686 argParser.add_argument('-D', '--define', action='append') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1687 argParser.add_argument('-d', '--dispatch', choices=('call', 'switch', 'goto'), default='call') |
e4fe5a450d05
Added option to CPU DSL to produce a threaded interpreter using computed goto
Michael Pavone <pavone@retrodev.com>
parents:
1748
diff
changeset
|
1688 parse(argParser.parse_args(argv[1:])) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1689 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1690 if __name__ == '__main__': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1691 from sys import argv |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1692 main(argv) |